Analog Devices Inc./Maxim Integrated DS33Z11+

Overview

DS33Z11+ from Maxim Integrated is a 10/100 Ethernet-to-TDM mapper IC that encapsulates IEEE 802.3 MAC frames into HDLC or X.86 (LAPS) for transport over synchronous PDH/TDM links up to 52Mbps. It supports MII/RMII Ethernet interfaces, features a programmable Committed Information Rate (CIR) controller with 512kbps granularity, and operates at 1.8V core with 3.3V-tolerant I/O-used in carrier-grade LAN extension over T1/E1, T3/E3, and DSL infrastructure.

For engineers reviewing the DS33Z11+ datasheet, DS33Z11+ pinout, DS33Z11+ application, or DS33Z11+ equivalent, this device serves as a deterministic store-and-forward Ethernet mapper with hardware-mode operation, external SDRAM buffering, and JTAG debug support-critical for telecom edge equipment requiring precise bandwidth allocation and protocol transparency.

Technical Context

The DS33Z11+ implements a dual-domain architecture: an IEEE 802.3-compliant 10/100 MAC with full/half-duplex flow control and a synchronous TDM serial port supporting independent TX/RX timing. Its HDLC/X.86 mapper performs frame alignment, FCS generation, and interframe fill per configuration registers.

It integrates a CIR controller that enforces fractional bandwidth limits on the WAN transmit path in 512kbps increments, and includes a built-in BERT engine for serial interface diagnostics. Clocking is flexible: Ethernet interface supports MII (25MHz) or RMII (50MHz), while serial interface clocks range from 1.544MHz to 52MHz depending on line rate and framing.

Key Specifications

Pinout & Package

DS33Z11+ is housed in a 169-ball, 14mm × 14mm CSBGA package (package code: 56-G6035-001), with 1.0mm ball pitch and exposed thermal pad. Pin functions include dedicated MII/RMII signals (TXD[3:0], RXD[3:0], TX_EN, CRS, COL), serial interface lines (TXCLK, RXCLK, TXD, RXD, TXFS, RXFS), SDRAM control (RAS#, CAS#, WE#, BA[1:0]), microprocessor bus (D[15:0], A[19:0], RD#, WR#), SPI (SCLK, MOSI, MISO, SS#), and JTAG (TCK, TMS, TDI, TDO, TRST#).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet-to-TDM mapping applications.

Compared with DS33Z11+, DS33ZH11+ reduces PCB area and BOM count by removing MPU bus pins but eliminates runtime reconfiguration; ICS843002AG-01 offers tighter SONET integration but lacks the DS33Z11+'s TDM versatility, CIR granularity, and external memory scalability.

Availability

DS33Z11+ is available at Aetrix Electronics and suitable for telecom infrastructure, carrier-grade LAN extension, and Ethernet-over-TDM access equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for DS33Z11+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and digital ICs for communications, computing, and industrial systems-with emphasis on high-reliability, low-power, and signal-integrity-critical applications.

The DS33Z11+ belongs to Maxim's Ethernet-to-TDM mapper product line, engineered specifically for carrier-class transparent LAN extension over legacy and emerging TDM infrastructures-including xDSL, SONET/SDH, and PDH networks.

FAQ

What is the primary function of the DS33Z11+ in a network architecture?

The DS33Z11+ functions as an Ethernet-to-TDM mapper that converts IEEE 802.3 MAC frames into HDLC or X.86 (LAPS) packets for transport over synchronous TDM links such as T1/E1, T3/E3, or OC-1. It performs store-and-forward packet processing with full wire-speed capability, enabling transparent LAN extension across legacy telecom infrastructure without requiring protocol translation or routing intelligence. The DS33Z11+ maintains frame integrity, supports VLAN tagging, and delivers deterministic latency critical for carrier-grade services.

Does the DS33Z11+ support both MII and RMII Ethernet interfaces simultaneously?

No, the DS33Z11+ supports either MII or RMII-but not both simultaneously. The interface mode is selected at power-up via configuration pins (MODEC[1:0]) and cannot be changed dynamically. MII mode uses four data lines (TXD[3:0], RXD[3:0]) and operates at 25MHz, while RMII uses two data lines (TXD, RXD) at 50MHz. Both modes support full/half-duplex operation and automatic flow control, and the DS33Z11+ retains identical HDLC/X.86 mapping functionality regardless of interface choice.

How does the Committed Information Rate (CIR) controller in the DS33Z11+ operate?

The CIR controller in the DS33Z11+ enforces bandwidth limits on the WAN transmit path in fixed 512kbps increments, up to the full line rate. It operates as a leaky bucket policer that meters outgoing HDLC/X.86 frames before transmission, discarding or marking non-conforming packets based on configuration. This ensures predictable bandwidth allocation for multi-tenant services and prevents congestion in shared TDM backhaul. The DS33Z11+ implements CIR entirely in hardware-no host processor intervention is required once configured via registers or hardware pins.

Can the DS33Z11+ operate without an external microprocessor?

Yes, the DS33Z11+ supports autonomous hardware mode operation using dedicated MODEC and HWMODE pins to configure default behavior-including HDLC/X.86 parameters, CIR settings, and interface timing. In this mode, it boots directly from internal state machines and requires no external firmware or host CPU. The DS33Z11+ retains full functionality including store-and-forward buffering, BERT diagnostics, and JTAG access-even without a microprocessor-making it suitable for headless, space-constrained telecom edge devices.

What type of external memory does the DS33Z11+ interface with, and why is it required?

The DS33Z11+ interfaces with external 16MB, 100MHz SDRAM via a 16-bit data bus and full command/control signals (RAS#, CAS#, WE#, BA[1:0]). This memory is required for store-and-forward packet buffering to absorb jitter and latency variations between asynchronous Ethernet and synchronous TDM domains. The SDRAM enables deep queues-critical for handling bursty LAN traffic over fixed-rate TDM links-and supports simultaneous read/write operations for seamless full-duplex throughput at wire speed. The DS33Z11+ manages SDRAM arbitration internally; no host CPU involvement is needed for memory scheduling.