My Inquiry
My Account
Analog Devices Inc./Maxim Integrated DS4625P+100/100
- Part No.:
- DS4625P+100/100
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Programmable Timers and Oscillators
- Package:
- -
- Datasheet:
-
DS4625P+100/100.pdf
- Description:
- IC OSC CLOCK 100MHZ 10-LCCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,765
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS4625P+100/100 from Maxim Integrated is a dual-output, low-jitter clock oscillator with two independent 100MHz LVPECL outputs, integrated AT-cut crystal and low-noise PLL, housed in a 5.0mm × 3.2mm LCCC package. It operates from +3.3V ±10%, delivers <0.7ps RMS phase jitter (12kHz–20MHz), and supports industrial temperature range (−40°C to +85°C). Used as XGMII and PCIe reference clock source.
For engineers reviewing the DS4625P+100/100 datasheet, DS4625P+100/100 pinout, DS4625P+100/100 application, or DS4625P+100/100 equivalent, key selection criteria include dual-LVPECL output synchronization capability, supply noise rejection performance, startup time (≤1.0ms), frequency stability (±50ppm total), and OE-controlled output enable/disable functionality.
Technical Context
The DS4625P+100/100 integrates a fundamental-mode AT-cut quartz crystal, oscillator circuit, and low-noise bipolar SiGe PLL with programmable dividers (DIV M/N/P) to generate two independent LVPECL clock outputs. Its architecture ensures deterministic jitter accumulation remains below 26.3ps P-P at 100kHz supply noise offset.
Each output pair (OP1/ON1 and OP2/ON2) provides differential LVPECL signaling referenced to PECL_BIAS = VCC − 2.0V, with guaranteed differential voltage (0.595–0.710V), rise/fall times ≤200ps, and duty cycle 45–55%. The OE pin enables synchronous disable of both outputs with 100ns propagation delay.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Frequency Pair | 100.000MHz / 100.000MHz - dual identical outputs for synchronized clock domains |
| Phase Jitter (RMS) | <0.7ps (12kHz–20MHz) - meets stringent timing budgets for 10GbE and PCIe Gen3 |
| Supply Voltage | +3.3V ±10% (2.97V–3.63V) - compatible with standard industrial 3.3V rails |
| Frequency Stability | ±50ppm total (temp, aging, load, supply, initial) - ensures long-term system timing margin |
| Startup Time | 1.0ms max - defined from VCC ≥ VCCMIN to PLL lock; critical for fast-boot systems |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade embedded and networking equipment |
| Output Type | Dual LVPECL - requires external 50Ω termination to PECL_BIAS (VCC − 2.0V) |
Pinout & Package
DS4625P+100/100 uses a 10-pin ceramic LCCC (5.0mm × 3.2mm × 1.49mm) with exposed thermal pad (EP) requiring grounding. Pin 1 is OE; pins 4/5 and A3/A4 are differential LVPECL output pairs; pin 6 is VCC; pins 2/3 and EP are ground; A1/A2 are no-connect (must be grounded).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Active-high CMOS enable input | Internal 70–130kΩ pullup; drives both LVPECL outputs high-impedance when low |
| 2, 3 (GND) | Ground reference | Low-inductance return path for oscillator core and output drivers |
| 4 (OP1), 5 (ON1) | Differential LVPECL Output Pair 1 | 100MHz positive/negative outputs; require 50Ω termination to PECL_BIAS |
| 6 (VCC) | Power supply input | +3.3V ±10% supply; bypass with 0.01μF + 0.1μF near pin |
| A1, A2 (N.C.) | No internal connection | Must be connected to GND for mechanical stability and EMI control |
| A3 (OP2), A4 (ON2) | Differential LVPECL Output Pair 2 | 100MHz positive/negative outputs; electrically isolated from Pair 1 |
| EP (Exposed Pad) | Thermal and electrical ground | Required for thermal relief; must be soldered to solid GND plane |
Key Features
| Feature | Design Value |
|---|---|
| Integrated AT-cut crystal + PLL | Eliminates external crystal layout, reduces BOM count, and guarantees phase noise performance |
| LVPECL output drivers | Supports high-speed serial interfaces (PCIe, SAS, InfiniBand) with <200ps edge rates |
| OE-controlled output disable | Enables dynamic power gating; reduces ICC_OEZ to 80–115mA during standby |
| 5.0mm × 3.2mm LCCC package | Compact footprint compatible with dense PCB layouts; exposed pad improves thermal dissipation |
| Excellent PSNR | Accumulated deterministic jitter due to 1MHz supply noise is only 6.4ps (P-P) |
Applications
| XGMII Clock Source | PCIe® Reference Clock |
|---|---|
Use Scenario: Provides synchronized 100MHz clocks to XGMII interface between MAC and PHY in 10GbE switches. IC Role / Device Role / Timing Role: Dual-output LVPECL oscillator delivering matched-frequency, low-jitter clocks to TX/RX lanes. Use Value: Phase jitter <0.7ps RMS ensures bit-error-rate compliance under high-speed serial link margins. |
Use Scenario: Supplies reference clock to PCIe Gen2/Gen3 root complex and endpoint devices. IC Role / Device Role / Timing Role: Primary timing source meeting PCIe clock jitter specification (≤1.0ps RMS, 12kHz–20MHz). Use Value: ±50ppm total stability maintains link training reliability across temperature and voltage variation. |
| SAS/SATA Timing Module | InfiniBand™ Clock Distribution |
Use Scenario: Generates dual 100MHz clocks for SAS initiator/target controllers and SATA host adapters. IC Role / Device Role / Timing Role: Low-phase-noise oscillator supporting multi-lane storage interconnect timing. Use Value: Differential LVPECL outputs drive multiple receivers with minimal skew and crosstalk. |
Use Scenario: Distributes synchronized 100MHz clocks across InfiniBand switch fabric modules. IC Role / Device Role / Timing Role: Dual-output clock source enabling deterministic latency across switching planes. Use Value: OE pin allows coordinated clock gating during link retraining without board-level redesign. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LVPECL oscillator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D-GM | Programmable 2-output clock generator (I²C-configurable); wider frequency range (0.16–350MHz); higher integration (integrated LDOs, spread spectrum) | Requires configuration firmware; supports variable-frequency use cases (e.g., multi-protocol adaptability) | Choose for flexible frequency synthesis where DS4625P+100/100's fixed 100/100MHz is insufficient |
| AK210-100.000MHZ-T | Fixed dual-output LVPECL oscillator; same 100/100MHz pair; 5.0 × 3.2mm SMD package; phase jitter 0.8ps RMS (12kHz–20MHz) | Identical pinout and electrical interface; RoHS-compliant; lower cost but slightly higher jitter | Choose for cost-sensitive designs accepting 0.1ps higher jitter and verified drop-in replacement in existing layouts |
Compared with Si5332A-D-GM and AK210-100.000MHZ-T, DS4625P+100/100 offers best-in-class 0.7ps RMS jitter and guaranteed factory-trimmed stability, making it optimal for timing-critical 10GbE and PCIe applications where configurability is unnecessary.
Availability
DS4625P+100/100 is available at Aetrix Electronics and suitable for XGMII clocking, PCIe reference timing, and InfiniBand™ clock distribution requiring stable component supply, consistent parametric performance, and long-term industrial temperature operation.
Supply support for DS4625P+100/100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications.
The DS4625P+100/100 belongs to Maxim's high-performance clock oscillator product line, engineered specifically for low-jitter, dual-output timing in high-speed serial interconnects including PCIe, SAS, and 10GbE.
FAQ
What is the exact output frequency configuration of DS4625P+100/100?
The DS4625P+100/100 is factory-trimmed to deliver two identical 100.000MHz LVPECL output pairs (OP1/ON1 and OP2/ON2), as specified in the Ordering Information table. Both outputs operate simultaneously and are not independently configurable; their phase relationship is not guaranteed per datasheet Section "Detailed Description".
Does DS4625P+100/100 require external biasing for LVPECL outputs?
Yes, DS4625P+100/100 requires external PECL_BIAS at VCC − 2.0V (e.g., 1.3V when VCC = 3.3V) for proper LVPECL termination. Each differential output must be terminated with 50Ω to this bias voltage, as shown in the Typical Application Circuit on page 6 of the datasheet.
What is the maximum allowable supply ripple for DS4625P+100/100 to maintain 0.7ps RMS jitter?
DS4625P+100/100 maintains its 0.7ps RMS jitter specification under typical conditions; however, deterministic jitter due to supply noise is characterized in the datasheet: 6.4ps P-P at 1MHz, 26.3ps P-P at 100kHz. To preserve jitter performance, keep VCC ripple below 10mVP-P across 10kHz–10MHz bandwidth using proper decoupling (0.01μF + 0.1μF near VCC pin).
Can DS4625P+100/100 be used in automotive applications?
No, DS4625P+100/100 is rated for −40°C to +85°C industrial temperature range only and is not AEC-Q200 qualified. It lacks automotive-specific screening, extended temperature validation, or enhanced reliability testing required for automotive ECUs or ADAS timing modules.
Is the exposed pad (EP) on DS4625P+100/100 electrically connected internally?
No, the exposed pad (EP) on DS4625P+100/100 is not internally connected to any die node; it serves solely as a thermal relief structure. Per datasheet Pin Description, EP "must be connected to ground" for mechanical stability and thermal conduction - this is a mandatory PCB layout requirement, not an electrical signal path.
DS4625P+100/100 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- -
- Count:
- -
- Frequency:
- -
- Voltage - Supply:
- -
- Current - Supply:
- -
- Operating Temperature:
- -
- Supplier Device Package:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
DS4625P+100/100 FAQ
1.How can I place an order for DS4625P+100/100 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS4625P+100/100 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS4625P+100/100 reliable?
The price and inventory of DS4625P+100/100 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS4625P+100/100 is usually 5 days.
3.What payment methods are accepted for DS4625P+100/100?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS4625P+100/100 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS4625P+100/100?
DS4625P+100/100 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS4625P+100/100 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS4625P+100/100?
For technical support, including DS4625P+100/100 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS4625P+100/100 requirements.
6.How does Aetrix verify that DS4625P+100/100 is sourced from the original manufacturer or authorized distributors?
All DS4625P+100/100 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS4625P+100/100 meets industry standards.
7.What is the process for return or replacement of DS4625P+100/100?
All DS4625P+100/100 units undergo pre-shipment inspection (PSI). If there is an issue with DS4625P+100/100, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS4625P+100/100 part is unused and in its original packaging.
Return procedure for DS4625P+100/100:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS4625P+100/100 Tags
-
NE555DR
Texas Instruments
-
SA555DR
Texas Instruments
-
NA555DR
Texas Instruments
-
SE555DR
Texas Instruments
-
NE555P
Texas Instruments
-
CD4541BM96
Texas Instruments
-
CD4541BE
Texas Instruments
-
TLC555QDR
Texas Instruments
-
TLC555IDR
Texas Instruments
-
TLC555QDRQ1
Texas Instruments
-
TPL5010DDCR
Texas Instruments
-
TLC555CP
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
