Analog Devices Inc./Maxim Integrated DS4625P+150/150

Overview

DS4625P+150/150 from Maxim Integrated is a dual-output, low-jitter clock oscillator with two 150MHz LVPECL outputs, integrated AT-cut crystal and low-noise PLL, housed in a 5.0mm × 3.2mm LCCC package, operating from +3.3V ±10% across –40°C to +85°C, used in high-speed serial interconnects requiring precise timing synchronization.

For engineers reviewing the DS4625P+150/150 datasheet, DS4625P+150/150 pinout, DS4625P+150/150 application, or DS4625P+150/150 equivalent, key selection criteria include phase jitter <0.7ps RMS (12kHz–20MHz), output enable control via active-high OE, differential LVPECL drive capability, frequency stability of ±50ppm total, and RoHS-compliant ceramic LCCC packaging.

Technical Context

The DS4625P+150/150 integrates a fundamental-mode AT-cut crystal with a bipolar SiGe-based low-noise PLL architecture, generating two independent 150MHz LVPECL output pairs without guaranteed phase relationship. Its PLL uses a charge-pump phase-frequency detector (PFD), loop filter (LPF), and LC-VCO with programmable dividers (M/N/P) to synthesize outputs from the crystal reference.

Each LVPECL output pair (OP1/ON1 and OP2/ON2) is terminated at VCC – 2.0V bias, delivering differential voltage ≥0.595V with rise/fall times ≤200ps and duty cycle 45–55%. The OE pin controls both outputs simultaneously with 100ns propagation delay and internal 70–130kΩ pullup resistor.

Key Specifications

Pinout & Package

DS4625P+150/150 is packaged in a 10-pin ceramic LCCC (Leadless Chip Carrier) with exposed thermal pad (EP), measuring 5.0mm × 3.2mm × 1.49mm. Pin 1 is OE (active-high output enable); pins 4/5 and A3/A4 are LVPECL output pairs (OP1/ON1 and OP2/ON2); pin 6 is VCC; pins 2/3 and A1/A2 are GND or no-connect (N.C.) as marked; EP must be soldered to ground for thermal relief.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output LVPECL oscillator applications.

Compared with Si5338A-B-GM and AK212-0150.0000T, DS4625P+150/150 delivers optimal balance of jitter performance, integrated crystal reliability, and simple OE-based power management in a proven 3.3V industrial package-ideal for fixed-frequency, high-reliability serial interconnects where programmability adds no value.

Availability

DS4625P+150/150 is available at Aetrix Electronics and suitable for XGMII clock generation, InfiniBand subnet management, and SAS/SATA host adapter timing requiring stable component supply, consistent parametric performance, and long-term manufacturability assurance.

Supply support for DS4625P+150/150 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications, emphasizing low-noise, high-reliability performance in harsh environments.

The DS4625P+150/150 belongs to Maxim's high-performance clock oscillator product line, engineered specifically for low-jitter, dual-output timing in 10GbE, InfiniBand, and PCIe infrastructure-prioritizing integration, stability, and signal integrity over configurability.

FAQ

What is the exact output frequency configuration of DS4625P+150/150?

The DS4625P+150/150 is factory-configured to deliver two identical 150.000MHz LVPECL output pairs (OP1/ON1 and OP2/ON2). This fixed-frequency variant is specified in the Ordering Information table with top mark "6CC" and is not user-programmable. The device does not support frequency adjustment post-manufacture.

Does DS4625P+150/150 require an external crystal or loop filter components?

No. The DS4625P+150/150 integrates an AT-cut fundamental-mode crystal, oscillator circuit, and low-noise PLL within its monolithic LCCC package. No external crystal, capacitors, or loop filter components are needed-only standard power supply decoupling (0.01μF + 0.1μF) and proper LVPECL termination at VCC – 2.0V.

What is the function and behavior of the OE pin on DS4625P+150/150?

The OE (Output Enable) pin on DS4625P+150/150 is an active-high CMOS input with an internal 70–130kΩ pullup resistor. When OE is high (≥0.7 × VCC), both LVPECL output pairs are enabled. When OE is low (≤0.3 × VCC), outputs enter high-impedance state. Propagation delays are ≤100ns for both enable and disable transitions.

Is DS4625P+150/150 compliant with RoHS and lead-free soldering processes?

Yes. DS4625P+150/150 carries the "+" suffix indicating RoHS-compliant packaging per JESD97 category e4 (Au over Ni). It is compatible with both lead-based and lead-free soldering processes, including reflow up to +260°C for 10 seconds, as confirmed in the Absolute Maximum Ratings section.

How does DS4625P+150/150 achieve its 0.7ps RMS phase jitter specification?

The DS4625P+150/150 achieves 0.7ps RMS phase jitter (12kHz–20MHz) through a combination of low-noise bipolar SiGe PLL architecture, optimized charge-pump design, integrated AT-cut crystal with minimal aging drift, and careful RF layout isolation within the LCCC package. Measured at +25°C and +3.3V, this jitter level satisfies 10GbE and PCIe Gen2 reference clock requirements.