Analog Devices Inc./Maxim Integrated DS8023-RJX+
- Part No.:
- DS8023-RJX+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Specialized
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS8023-RJX+.pdf
- Description:
- IC INTERFACE SPECIALIZED 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:239
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Product details
Overview
The DS8023-RJX+ from Maxim Integrated is a smart card interface IC designed as an analog front-end for ISO 7816, EMV, and GSM11-11 compliant readers. It supports 5V, 3V, and 1.8V smart cards; delivers up to 80mA at 5V with ±8kV IEC ESD protection on card pins; and achieves ultra-low stop-mode current of <10nA (typ). It serves in banking terminals, POS systems, and ATMs where secure, low-power, multi-voltage card interfacing is required.
For engineers reviewing the DS8023-RJX+ datasheet, DS8023-RJX+ pinout, DS8023-RJX+ application, or DS8023-RJX+ equivalent, key selection considerations include its 28-pin TSSOP package, triple-voltage VCC generation (5V/3V/1.8V), integrated charge pump, automatic activation/deactivation sequencer, and compatibility with NXP TDA8024-based designs.
Technical Context
The DS8023-RJX+ integrates a voltage supervisor, charge-pump-based card supply generator, flexible clock divider (×1/2/4/8), and synchronized I/O transceivers with 11kΩ internal pullups. Its control sequencer autonomously manages activation (tACT = 160μs) and deactivation (tDEACT = 80μs) sequences upon CMDVCC assertion, eliminating host timing-critical software overhead.
It features dual card presence inputs (PRES active-low and PRES active-high), fault detection for short-circuit, overtemperature (>150°C shutdown), and VDD dropout, plus 8ms hardware debounce on PRES. The OFF interrupt pin signals card insertion, removal, or fault conditions with status-latched behavior during card sessions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Digital Supply (VDD) | 2.7V to 6.0V - powers host-side logic and interfaces; must match host MCU supply. |
| Card Supply Outputs | 5.0V ±5% / 80mA max, 3.0V ±8% / 65mA max, 1.8V ±10% / 30mA max - fully regulated, charge-pump generated. |
| Stop-Mode Current | <10nA (typ) - entered by holding CMDVCC, 5V/3V, and 1_8V high; enables battery-backed standby. |
| ESD Protection | ±8kV (min), IEC 61000-4-2 - protects card-contact pins (I/O, CLK, RST, AUX1/AUX2) without external TVS. |
| Clock Input Range | 0–20MHz crystal or external clock on XTAL1/XTAL2 - supports ISO-compliant CLK frequencies via programmable dividers. |
| I/O Line Max Frequency | 1MHz - sufficient for T=0/T=1 protocols; includes active pullup (tPU = 100ns) for fast low-to-high transitions. |
| Operating Temp | −40°C to +85°C - qualified for industrial and commercial reader environments including ATMs and POS terminals. |
Pinout & Package
DS8023-RJX+ is housed in a 28-pin Thin Shrink Small Outline Package (TSSOP) with 0.65mm pitch, thermally enhanced for embedded reader applications. Pin 1 is located at the top-left corner (marking dot adjacent), with pins numbered counter-clockwise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 (CLKDIV1, CLKDIV2) | Clock Divider Control | Selects CLK output frequency: fXTAL/8, /4, /2, or /1 - determines smart card clock rate per ISO 7816-3. |
| 3 (5V/3V) | VCC Selection Input | Logic-high = 5V card mode; logic-low = 3V card mode - overridden by 1_8V when asserted. |
| 4 (PGND) | Analog Ground Reference | Separate ground for charge pump and analog circuitry; must be connected to system analog ground plane. |
| 5, 7 (CP2, CP1) | Charge-Pump Capacitor Terminals | Connect 100nF ceramic capacitor (ESR < 100mΩ) between CP1–CP2 to enable voltage doubling/following. |
| 6 (VDDA) | Charge-Pump Supply Input | Must be ≥ VDD and ≥3.0V; supplies internal regulator generating VCC - critical for stable 5V/3V/1.8V outputs. |
| 8 (VUP) | Charge-Pump Output | Connects to 100nF capacitor to GND; provides boosted voltage for internal regulation stages. |
| 9, 10 (PRES, PRES) | Card Presence Inputs | Active-low and active-high inputs - debounced internally (8ms typ); drive OFF interrupt after stabilization. |
| 11 (I/O) | Smart Card Data Line (C7) | Level-shifted bidirectional data path to card contact C7; includes 11kΩ pullup to VCC in inactive state. |
| 12, 13 (AUX2, AUX1) | Auxiliary Card Lines (C8, C4) | Identical to I/O - support C4/C8 auxiliary functions per ISO 7816; share same transceiver architecture. |
| 14 (CGND) | Smart Card Ground Return | Dedicated low-impedance return path for card contacts; must be routed separately from digital/analog grounds. |
| 15 (CLK) | Smart Card Clock Output (C3) | Programmable-frequency clock to contact C3; meets ISO 7816-3 duty cycle (45–55%) and slew rate specs. |
| 16 (RST) | Smart Card Reset Output (C2) | Controlled reset signal to contact C2; driven low during deactivation and emergency fault shutdown. |
| 17 (VCC) | Smart Card Supply Voltage | Output delivering selected 5V/3V/1.8V to contact C1; decoupled with 2×100nF or 100nF+220nF near connector. |
| 18 (1_8V) | 1.8V Override Input | Active-high forces 1.8V VCC regardless of 5V/3V state - enables backward-compatible upgrade paths. |
| 19 (CMDVCC) | Activation Sequence Trigger | Active-low initiates full card activation sequence (power-up, clock, reset, I/O enable) - synchronous with internal sequencer. |
| 20 (RSTIN) | Host Reset Input | Directly controls RST output after t5 in activation; used for precise ATR timing or alternate activation flow. |
| 21 (VDD) | Digital Supply Input | Main supply for host-side logic; must match host MCU VDD to ensure level compatibility on all control pins. |
| 22 (GND) | Digital Ground | Reference for VDD, control inputs (CLKDIVx, 5V/3V, CMDVCC, etc.), and I/OIN/AUXxIN lines. |
| 23 (OFF) | Status Interrupt Output | Active-low open-drain output indicating card presence, removal, or fault - pulled up to VDD via 20kΩ internal resistor. |
| 24, 25 (XTAL1, XTAL2) | Crystal/Clock Input | Accepts 20MHz max crystal or external clock; XTAL1 also accepts buffered clock input for low-idle-current variants. |
| 26 (I/OIN) | Host-to-IC Data Input | Host-side I/O line; transceiver master/slave arbitration ensures correct directionality without external logic. |
| 27, 28 (AUX1IN, AUX2IN) | Host Auxiliary Inputs | Match I/OIN function for C4/C8 host communication; identical electrical characteristics and arbitration behavior. |
Key Features
| Feature | Design Value |
|---|---|
| Triple-Voltage Smart Card Power Generation | On-chip charge pump delivers stable 5V/3V/1.8V VCC with load regulation - eliminates need for external LDOs or switching regulators. |
| Hardware-Controlled Activation/Deactivation Sequencing | Internal sequencer executes ISO-compliant power-up (160μs) and power-down (80μs) without host CPU intervention - reduces firmware complexity and timing risk. |
| Integrated 8ms Hardware Debounce | Eliminates mechanical switch bounce on card-insertion detection - prevents false OFF assertions and spurious deactivations. |
| Ultra-Low Stop-Mode Power | <10nA consumption achieved by disabling all analog blocks while preserving PRES monitoring - extends battery life in portable readers. |
| Synchronized Clock Divider with Glitch-Free Transitions | Frequency changes (fXTAL/1→/2→/4→/8) occur synchronously with no sub-cycle pulses - ensures compliance with EMV and ISO clock stability requirements. |
Applications
| Banking Payment Terminals | POS & PIN Pad Systems |
|---|---|
Use Scenario: Secure debit/credit transaction processing in countertop or handheld payment devices requiring EMV Level 1 certification. IC Role / Device Role / Timing Role: Analog front-end managing VCC sequencing, CLK generation, RST timing, and I/O level-shifting per ISO 7816-3 and EMV 2000. Use Value: Enables single-chip replacement of legacy TDA8024 with minimal layout change and built-in fault handling for field-reliable operation. | Use Scenario: Multi-interface point-of-sale terminals supporting contact smart cards, magnetic stripe, and NFC coexistence. IC Role / Device Role / Timing Role: Provides isolated, ESD-hardened card interface with independent 1.8V/3V/5V support - avoids voltage conflict when multiple card types are inserted. Use Value: Reduces BOM count by integrating charge pump, sequencer, and transceivers - simplifies compliance testing across card voltage classes. |
| Automated Teller Machines (ATMs) | Conditional Access Set-Top Boxes |
Use Scenario: High-availability financial kiosks operating 24/7 in unattended environments with strict thermal and reliability requirements. IC Role / Device Role / Timing Role: Smart card interface with overtemperature shutdown (>150°C), short-circuit protection, and robust VDD supervision - ensures fail-safe card ejection. Use Value: Prevents card lockup or damage during power brownouts or connector faults - improves mean time between failures (MTBF). | Use Scenario: Pay-TV conditional access modules validating subscriber smart cards in residential STBs with space-constrained PCB layouts. IC Role / Device Role / Timing Role: Low-power card interface enabling deep-sleep modes (stop mode <10nA) while retaining card presence detection - supports instant-on UX. Use Value: Eliminates need for external wake-up circuitry - reduces standby power to sub-μW levels without sacrificing responsiveness. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar smart card interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP TDA8024 | Lacks 1.8V support and stop-mode; uses PORADJ instead of 1_8V pin; no integrated 8ms debounce. | Requires external 1.8V regulator and debounce RC network; not suitable for modern low-voltage cards without redesign. | Use only for legacy TDA8024 drop-in replacements where 1.8V cards are not required. |
| Infineon SLE 66CX2100P | Integrated microcontroller core; requires firmware development; higher active current (≈2mA vs. DS8023's 35mA active-only). | Targets embedded secure controller applications; not a pure analog front-end - adds software validation overhead. | Select when secure execution environment or cryptographic acceleration is needed beyond interface functionality. |
Compared with NXP TDA8024 and Infineon SLE 66CX2100P, the DS8023-RJX+ delivers verified 1.8V/3V/5V support, certified ±8kV ESD, and hardware-automated sequencing - reducing design risk and qualification effort for ISO/EMV-certified readers.
Availability
DS8023-RJX+ is available at Aetrix Electronics and suitable for banking payment terminals, POS systems, and automated teller machines requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for DS8023-RJX+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in precision analog, mixed-signal, and power management ICs for industrial, communications, and consumer applications.
The DS8023-RJX+ belongs to Maxim's secure interface product line, engineered specifically for ISO 7816-compliant smart card readers demanding low power, multi-voltage support, and robust fault tolerance in commercial and financial infrastructure.
FAQ
What is the primary function of the DS8023-RJX+ in a smart card reader system?
The DS8023-RJX+ serves as the analog front-end interface between a host microcontroller and ISO 7816 smart cards. It generates and regulates card supply voltages (5V/3V/1.8V), provides level-shifted bidirectional I/O, drives CLK and RST signals, detects card presence, and executes autonomous activation/deactivation sequences - all within a single 28-pin TSSOP package. Its integration eliminates discrete voltage regulators, level shifters, and protection components required in earlier designs.
How does the DS8023-RJX+ support 1.8V smart cards, and what pin controls this?
The DS8023-RJX+ supports 1.8V smart cards via its dedicated 1_8V input pin (Pin 18). When this pin is driven high, it overrides the 5V/3V selection and configures the internal charge-pump regulator to deliver 1.8V ±10% at up to 30mA to the VCC pin. This capability enables direct compatibility with modern low-voltage cards without external circuitry - a key differentiator from legacy alternatives like the TDA8024, which lacks native 1.8V support.
What is the purpose of the OFF pin on the DS8023-RJX+, and how does it behave during card insertion?
Pin 23 (OFF) is an active-low open-drain interrupt output signaling card presence, removal, or fault conditions. During card insertion, the DS8023-RJX+ applies 8ms hardware debounce to the PRES inputs; once stabilized, OFF transitions high to indicate valid card presence. If a fault occurs during an active session (e.g., short circuit or overtemperature), OFF asserts low to trigger emergency deactivation. Its internal 20kΩ pullup to VDD simplifies host connection with no external resistor required.
Can the DS8023-RJX+ replace the NXP TDA8024, and what design changes are needed?
Yes, the DS8023-RJX+ is explicitly positioned as a functional upgrade to the TDA8024, with many designs requiring minimal hardware changes. Key differences include replacement of the TDA8024's PORADJ pin with the DS8023-RJX+'s 1_8V pin, removal of external debounce components (integrated 8ms debounce), and addition of stop-mode control (CMDVCC/5V/3V/1_8V high). Software must be updated to manage the new 1_8V pin and optionally enable ultra-low-power stop mode.
What are the absolute maximum ratings for VDD and VDDA on the DS8023-RJX+?
The DS8023-RJX+ has an absolute maximum VDD rating of −0.5V to +6.5V relative to GND, and VDDA rating of −0.5V to +6.5V relative to PGND. Exceeding these limits may cause permanent damage. For reliable operation, VDD must be maintained between 2.7V and 6.0V, and VDDA must be ≥ VDD and ≥3.0V (up to 6.0V). These ranges ensure proper charge-pump operation and stable VCC generation across all supported smart card voltages.
DS8023-RJX+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Smart Card
- Interface:
- Analog
- Voltage - Supply:
- 2.7V ~ 6V
- Supplier Device Package:
- 28-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS8023-RJX+ FAQ
1.How can I place an order for DS8023-RJX+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS8023-RJX+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS8023-RJX+ reliable?
The price and inventory of DS8023-RJX+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS8023-RJX+ is usually 5 days.
3.What payment methods are accepted for DS8023-RJX+?
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Note: Certain payment methods may incur a processing fee.
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DS8023-RJX+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS8023-RJX+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS8023-RJX+?
For technical support, including DS8023-RJX+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS8023-RJX+ requirements.
6.How does Aetrix verify that DS8023-RJX+ is sourced from the original manufacturer or authorized distributors?
All DS8023-RJX+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS8023-RJX+ meets industry standards.
7.What is the process for return or replacement of DS8023-RJX+?
All DS8023-RJX+ units undergo pre-shipment inspection (PSI). If there is an issue with DS8023-RJX+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS8023-RJX+ part is unused and in its original packaging.
Return procedure for DS8023-RJX+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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