Analog Devices Inc./Maxim Integrated DS8024-RJX/V+
- Part No.:
- DS8024-RJX/V+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Specialized
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS8024-RJX/V+.pdf
- Description:
- IC INTERFACE SPECIALIZED 28TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS8024-RJX/V+ from Maxim Integrated is a smart card interface IC serving as an analog front-end for ISO 7816, EMV®, and GSM11-11 compliant readers. It delivers 5.0V ±5% (80mA max) and 3.0V ±8% (65mA max) card supply voltages, supports flexible clock division (÷1/2/4/8), and provides ±8kV IEC ESD protection on card interfaces. It operates across -40°C to +85°C in automotive-qualified 28-pin TSSOP.
For engineers reviewing the DS8024-RJX/V+ datasheet, DS8024-RJX/V+ pinout, DS8024-RJX/V+ application, or DS8024-RJX/V+ equivalent, key selection considerations include its dual-voltage card power generation, automatic activation/deactivation sequencing, integrated charge pump, fault detection (short-circuit, overtemperature, VDD dropout), and drop-in compatibility with NXP TDA8024 in identical packages.
Technical Context
The DS8024-RJX/V+ integrates a voltage supervisor with 220µs internal reset pulse (tW), a programmable crystal oscillator supporting up to 20MHz input and configurable CLK output (fXTAL/1, /2, /4, /8), and a dual-mode charge pump (1x/2x) that adapts based on VDDA and selected card voltage (3V/5V). Its control sequencer autonomously manages activation (tACT = 160µs) and deactivation (tDEACT = 80µs) timing without host intervention beyond CMDVCC and RSTIN.
It features three bidirectional transceivers (I/O, AUX1, AUX2) with 11kΩ internal pullups to VCC/VDD, active pullup logic for fast low-to-high transitions, and current limiting (±15mA) on all data lines. Fault response differs by mode: OFF asserts low only during active-card faults (e.g., short-circuit, overheating at +150°C), while card presence is debounced with 8ms typical delay on PRES/PRES inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Digital Supply Voltage (VDD) | 2.7V to 6.0V - Enables direct interfacing with 3.3V or 5V host controllers without level-shifting circuitry. |
| Card Supply Voltage (VCC) | 5.0V ±5% (80mA max) or 3.0V ±8% (65mA max) - Programmable via 5V/3V pin; supports both legacy and modern smart cards. |
| Clock Input Frequency | 0–20MHz external crystal or clock on XTAL1/XTAL2 - Provides full ISO/EMV timing compliance with selectable division ratios. |
| ESD Protection | ±8kV (min) per IEC 61000-4-2 on card interfaces - Eliminates need for external TVS diodes on C2/C3/C7 contacts. |
| Activation Time | tACT = 160µs - Guarantees controlled VCC ramp, CLK enable, and RST assertion sequence for reliable ATR acquisition. |
| Deactivation Time | tDEACT = 80µs - Ensures safe, sequenced shutdown (RST low → CLK low → I/O pull-low → VCC discharge) to prevent card corruption. |
| Operating Temperature | -40°C to +85°C - Automotive-qualified variant meets AEC-Q100 stress test requirements for in-vehicle payment systems. |
Pinout & Package
DS8024-RJX/V+ is housed in a RoHS-compliant, automotive-qualified 28-pin Thin Shrink Small Outline Package (TSSOP) with 0.65mm pitch and exposed thermal pad (not electrically connected). The package supports standard reflow soldering (260°C peak) and achieves 1117.3mW power dissipation at +70°C ambient.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 CLKDIV1, CLKDIV2 | Clock divider select inputs | Set CLK output frequency as fXTAL/1, /2, /4, or /8 - critical for matching card ATR clock requirements. |
| 3 5V/3V | Card voltage selection | Logic-high = 5V card mode; logic-low = 3V card mode - determines charge pump operating mode and VCC regulation target. |
| 4 PGND | Analog ground reference | Separate ground for charge pump and card voltage generator - prevents digital noise coupling into VCC rail. |
| 5, 7 CP2, CP1 | Charge-pump capacitor terminals | Connect 100nF capacitor (ESR < 100mΩ) between CP1–CP2 - forms core of voltage-doubling stage for 3V operation. |
| 6 VDDA | Charge-pump supply input | Must be ≥ VDD and ≥3.3V - powers internal regulator; determines 1x/2x mode selection for VCC generation. |
| 8 VUP | Charge-pump output | Connect 100nF capacitor to GND - stabilizes boosted internal rail used for VCC regulation. |
| 9, 10 PRES, PRES | Active-low / active-high card presence inputs | Dual-input design accommodates normally-open or normally-closed mechanical switches - enables robust insertion/extraction detection with 8ms debounce. |
| 11 I/O | Smart card data line (C7) | Bidirectional transceiver with 11kΩ pullup to VCC - handles T=0/T=1 protocol data exchange with automatic master/slave arbitration. |
| 12, 13 AUX2, AUX1 | Smart card auxiliary lines (C8, C4) | Identical to I/O - supports extended command sets and proprietary card functions requiring C4/C8 signaling. |
| 14 CGND | Smart card ground (C5) | Dedicated low-impedance return path for card contacts - must be routed separately from PGND/GND to minimize noise coupling. |
| 15 CLK | Smart card clock output (C3) | Programmable frequency output with 45–55% duty cycle - meets ISO 7816-3 timing jitter <100ps when layout guidelines are followed. |
| 16 RST | Smart card reset output (C2) | Driven low during activation/deactivation sequences - initiates card cold/warm reset per EMV Level 1 timing. |
| 17 VCC | Smart card supply voltage output (C1) | Regulated 3V or 5V output with overload detection at ~120mA - supports pulsed currents up to 200mA (400ns) without false trip. |
| 18 N.C. | No connection | Unused pin - must be left floating or tied to GND; no internal connection or function. |
| 19 CMDVCC | Activation sequence trigger | Active-low input - initiates full activation sequence (VCC ramp, CLK enable, RST assert) when pulled low by host MCU. |
| 20 RSTIN | Host reset input | Allows host-controlled CLK timing - RSTIN high during CMDVCC low delays CLK start until RSTIN is pulled low between t3 and t5. |
| 21 VDD | Digital supply input | Main power for digital logic and I/O transceivers - must match host controller supply voltage (2.7–6.0V). |
| 22 GND | Digital ground | Reference for VDD, control pins, and host-side I/O - requires star-point connection with PGND and CGND to avoid ground loops. |
| 23 OFF | Status interrupt output | Active-low open-drain output with 20kΩ internal pullup - signals card presence (high) or fault condition (low) during active session. |
| 24, 25 XTAL1, XTAL2 | Crystal/clock input | Accepts 20MHz crystal or external clock - XTAL1 is single-ended input; XTAL2 is crystal complement; oscillator runs continuously after power-up. |
| 26 I/OIN | Host-to-IC data line | Input side of I/O transceiver - pulled high to VDD via 11kΩ resistor; participates in edge arbitration with I/O pin. |
| 27, 28 AUX1IN, AUX2IN | Host-to-IC auxiliary lines | Input sides of AUX1/AUX2 transceivers - identical electrical behavior to I/OIN; support C4/C8 host commands. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual-voltage card power generator | Eliminates need for external LDOs or switching regulators - reduces BOM count and PCB area while maintaining ±5% 5V and ±8% 3V accuracy under load. |
| Automatic activation/deactivation sequencer | Hardware-controlled timing (tACT = 160µs, tDEACT = 80µs) ensures ISO/EMV-compliant power-up/down without host firmware overhead or timing-critical software delays. |
| Dedicated card presence detection with debounce | Supports both normally-open and normally-closed socket switches via dual PRES inputs - 8ms hardware debounce prevents false card-insertion/extraction events. |
| Fault detection and emergency deactivation | Monitors VCC short-circuit, VDD dropout, and temperature (>150°C); triggers immediate deactivation and pulls OFF low only during active sessions - isolates faults without disrupting host operation. |
| Pin-for-pin replacement for NXP TDA8024 | Direct drop-in upgrade path - identical 28-pin TSSOP/SO footprint and functional mapping (excluding PORADJ pin omission) minimizes redesign effort and qualification time. |
Applications
| Banking Payment Terminals | Automated Teller Machines (ATMs) |
|---|---|
|
Use Scenario: Secure debit/credit card transactions at point-of-sale using EMV Level 1 certified readers. IC Role / Device Role: Analog front-end managing VCC, CLK, RST, and I/O signal translation between host MCU and ISO 7816 smart card. Use Value: Delivers ±8kV ESD protection and regulated 5V/3V VCC to ensure ATR reliability and prevent card damage during repeated insertion cycles. |
Use Scenario: High-availability cash dispensing systems requiring continuous operation in uncontrolled environments. IC Role / Device Role: Smart card interface with automotive-grade temperature range (-40°C to +85°C) and fault detection for fail-safe card handling. Use Value: Emergency deactivation on VCC short-circuit or overheating prevents card lockup and enables automatic recovery without host intervention. |
| Set-Top Box Conditional Access | Telecommunications SIM Readers |
|
Use Scenario: Pay-TV decryption modules validating subscriber smart cards in consumer electronics enclosures. IC Role / Device Role: Low-cost interface supporting both 3V and 5V cards via 5V/3V pin selection and flexible clock division for diverse card ATR requirements. Use Value: Integrated charge pump eliminates external DC-DC converter - reduces solution cost and EMI emissions in space-constrained STB designs. |
Use Scenario: Field-deployable telecom equipment reading GSM11-11 compliant SIM cards in base stations or provisioning tools. IC Role / Device Role: Robust card presence detection using dual PRES inputs and 8ms hardware debounce to tolerate mechanical switch bounce in ruggedized enclosures. Use Value: OFF pin provides unambiguous status indication - high = card present/inactive, low = fault detected during active session - simplifies host error logging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar smart card interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP TDA8024 | Pin-compatible but includes PORADJ pin for adjustable reset threshold; lacks DS8024's integrated 20kΩ OFF pullup. | Legacy industrial designs where PORADJ tuning is required; not automotive-qualified. | Select TDA8024 only if existing layout uses PORADJ; otherwise DS8024-RJX/V+ offers superior integration and AEC-Q100 compliance. |
| Maxim DS8113 | Lower active/stop-mode power consumption; adds true low-power stop mode; different pinout and package (24-pin TSSOP). | Portable/battery-powered readers requiring <500μA inactive current; incompatible PCB footprint. | Choose DS8113 only for battery-operated devices; DS8024-RJX/V+ remains optimal for mains-powered, automotive-grade readers needing full feature set. |
Compared with NXP TDA8024, DS8024-RJX/V+ removes PORADJ but adds integrated OFF pullup and automotive qualification; compared with DS8113, it trades lower power for pin compatibility, broader voltage support, and identical TSSOP footprint - making it the preferred choice for drop-in upgrades in fixed-power, high-reliability applications.
Availability
DS8024-RJX/V+ is available at Aetrix Electronics and suitable for banking payment terminals, automated teller machines, and set-top box conditional access systems requiring stable component supply, automotive-grade temperature performance, and long-term lifecycle availability.
Supply support for DS8024-RJX/V+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in precision analog, mixed-signal, and power management ICs for industrial, communications, and computing applications.
The DS8024-RJX/V+ belongs to Maxim's secure transaction interface product line, designed specifically for ISO 7816/EMV/GSM11-11 smart card readers requiring robust analog front-end functionality, fault resilience, and automotive qualification.
FAQ
What is the operating temperature range for DS8024-RJX/V+?
The DS8024-RJX/V+ is rated for -40°C to +85°C operation and is explicitly qualified for automotive applications, as indicated by the "/V" suffix in its part number. This rating is guaranteed per Maxim's datasheet Rev 4 and aligns with AEC-Q100 stress testing requirements for in-vehicle deployment scenarios such as telematics-based payment systems.
Does DS8024-RJX/V+ support both 3V and 5V smart cards?
Yes, DS8024-RJX/V+ supports both 3V and 5V smart cards via the dedicated 5V/3V pin (Pin 3). When logic-high, it configures the internal charge pump and regulator to deliver 5.0V ±5% (80mA max); when logic-low, it delivers 3.0V ±8% (65mA max). This selection is hardware-controlled and does not require host firmware changes.
How does DS8024-RJX/V+ handle card insertion and removal?
DS8024-RJX/V+ uses dual PRES inputs (Pins 9 and 10) to detect card presence with hardware debounce (8ms typical). Insertion pulls one PRES line active, triggering OFF to go high after debounce; removal causes immediate emergency deactivation and pulls OFF low. The sequencer executes full ISO-compliant activation (160µs) and deactivation (80µs) automatically.
Is DS8024-RJX/V+ a pin-for-pin replacement for NXP TDA8024?
Yes, DS8024-RJX/V+ is a documented pin-for-pin drop-in replacement for NXP TDA8024 in 28-pin TSSOP and SO packages. All signal names, pin locations, and electrical characteristics match, except DS8024 omits the PORADJ pin. No PCB layout changes are required, and existing firmware operates unchanged.
What fault conditions does DS8024-RJX/V+ monitor and how does it respond?
DS8024-RJX/V+ monitors VCC short-circuit, VDD dropout below threshold, card voltage generator overload (~120mA), and die temperature (>150°C). During active sessions (CMDVCC low), any fault pulls OFF low and triggers automatic emergency deactivation. Outside sessions, only card presence affects OFF state - ensuring clean fault isolation.
DS8024-RJX/V+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Smart Card
- Interface:
- Analog
- Voltage - Supply:
- -
- Supplier Device Package:
- 28-TSSOP
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
DS8024-RJX/V+ FAQ
1.How can I place an order for DS8024-RJX/V+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS8024-RJX/V+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS8024-RJX/V+ reliable?
The price and inventory of DS8024-RJX/V+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS8024-RJX/V+ is usually 5 days.
3.What payment methods are accepted for DS8024-RJX/V+?
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4.How is shipping managed for DS8024-RJX/V+?
DS8024-RJX/V+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS8024-RJX/V+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS8024-RJX/V+?
For technical support, including DS8024-RJX/V+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS8024-RJX/V+ requirements.
6.How does Aetrix verify that DS8024-RJX/V+ is sourced from the original manufacturer or authorized distributors?
All DS8024-RJX/V+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS8024-RJX/V+ meets industry standards.
7.What is the process for return or replacement of DS8024-RJX/V+?
All DS8024-RJX/V+ units undergo pre-shipment inspection (PSI). If there is an issue with DS8024-RJX/V+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS8024-RJX/V+ part is unused and in its original packaging.
Return procedure for DS8024-RJX/V+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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