My Inquiry
My Account
Analog Devices Inc./Maxim Integrated DS80C390-QNR
- Part No.:
- DS80C390-QNR
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Microcontrollers
- Package:
- 68-LCC (J-Lead)
- Datasheet:
-
DS80C390-QNR.pdf
- Description:
- IC MCU 8BIT ROMLESS 68PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,441
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS80C390-QNR from Maxim Integrated (now Analog Devices) is a high-speed 8051-compatible microcontroller with dual CAN 2.0B controllers, 4kB internal SRAM, and hardware math accelerator. It executes 8051 instructions up to 3× faster than standard 8051 at same crystal frequency, supports 40MHz max crystal (≈100MHz apparent execution), and operates from -40°C to +85°C in 68-pin PLCC package. It targets industrial control systems requiring deterministic real-time CAN communication and embedded processing.
For engineers reviewing the DS80C390-QNR datasheet, DS80C390-QNR pinout, DS80C390-QNR application, or DS80C390-QNR equivalent, this page delivers verified technical context, validated pin functions, confirmed CAN 2.0B controller behavior, exact memory architecture details (22-bit addressing, multiplexed/nonmultiplexed bus modes), and real-world selection guidance against functionally comparable alternatives.
Technical Context
The DS80C390-QNR implements a redesigned 8051 core executing instructions in 4 clock cycles per machine cycle (vs. 12 in legacy 8051), enabling single-cycle instruction execution in 100ns at 40MHz. Its dual independent CAN 2.0B controllers each support 15 message objects, 11-bit/29-bit identifiers, DeviceNet™/SDS protocol compatibility, and SIESTA low-power mode.
It integrates two full-duplex UARTs (one with programmable IrDA clock), a hardware 16/32-bit math coprocessor for multiply/divide/shift/accumulate, and configurable memory interface supporting up to 4MB external address space via 22-bit program/data counter - selectable between paged, contiguous, or legacy 8051-compatible modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 8051-compatible, 4-clock-per-machine-cycle execution (3× speed vs. legacy 8051) |
| Max Clock Frequency | 40MHz crystal input → ≈100MHz effective instruction throughput |
| Internal Memory | 4kB SRAM usable as program, data, or stack memory - no external ROM required for basic boot |
| CAN Controllers | Dual independent CAN 2.0B controllers, each with 15 message objects and SIESTA low-power mode |
| Serial Interfaces | Two full-duplex UARTs; one supports programmable IrDA clock for infrared communication |
| Operating Temperature | -40°C to +85°C - qualified for industrial and automotive under-hood environments |
| Package | 68-pin PLCC - lead-free/RoHS-compliant (QNR+ variant), with thermal and mechanical stability for reflow soldering |
Pinout & Package
DS80C390-QNR is housed in a 68-pin Plastic Leaded Chip Carrier (PLCC) package, offering robust thermal performance and reliable socketing for prototyping and industrial deployment. Pin assignments are identical across all DS80C390 variants in PLCC form factor.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pins 17,32,51,68) | Power Supply | +5V digital supply; four dedicated pins reduce IR drop and improve noise immunity in high-speed operation |
| GND (Pins 1,18,35,52) | Ground Reference | Digital ground return; multiple pins minimize ground bounce during simultaneous I/O switching |
| P5.0–P5.3 (Pins 31–28) | CAN Interface | C0TX/C0RX/C1TX/C1RX - dedicated differential CAN transceiver I/O; require external CAN transceivers (e.g., MAX3051) |
| P3.6–P3.7 (Pins 19–22) | Memory Control | WR/RD strobes - drive external data memory with precise timing compatible with 74-series latches and SRAM |
| ALE (Pin 57) | Address Latch Enable | Outputs 1.5-cycle pulse every 4 XTAL1 cycles to latch Port 0 LSB in multiplexed mode; configurable toggle in demux mode |
| EA (Pin 52) | External Access | Must be tied to GND - forces all code fetches from external memory; no internal ROM present |
| RSTOL (Pin 33) | Reset Output | Active-low signal asserted during power-on reset, watchdog timeout, oscillator failure, or VCC ≤ 4.13V |
Key Features
| Feature | Design Value |
|---|---|
| Hardware Math Accelerator | Accelerates 16/32-bit multiply, divide, shift, normalization, and accumulate operations - critical for real-time PID control loops |
| Dual CAN 2.0B Controllers | Each supports 11-bit/29-bit IDs, 15 message buffers, and SIESTA mode - enables redundant or multi-bus CAN networks without host CPU overhead |
| Configurable Memory Interface | Supports multiplexed (Port 0 AD0–7) or nonmultiplexed (Port 0 D0–7 + Port 1 A0–7) bus modes - simplifies migration from legacy 8051 designs |
| Frequency Multiplier | Internal PLL allows full-speed operation with lower-frequency crystals (e.g., 10MHz → 40MHz core) - reduces EMI and eases EMC compliance |
| 22-Bit Addressing | User-enabled 22-bit program/data counter expands external memory access to 4MB - supports complex firmware and data logging in resource-constrained systems |
Applications
| Industrial Motion Control | Factory Automation Gateway |
|---|---|
Use Scenario: Real-time coordination of servo drives, limit switches, and safety interlocks in CNC machinery. IC Role / Device Role / Timing Role: Primary controller executing motion profiles, managing dual CAN buses for drive feedback and HMI commands, and handling time-critical interrupts (INT0–INT5). Use Value: 100ns single-cycle instructions and deterministic CAN message scheduling ensure sub-millisecond jitter in closed-loop control. |
Use Scenario: Protocol translation between Modbus RTU field devices and EtherNet/IP supervisory systems. IC Role / Device Role / Timing Role: Dual-CAN interface bridges legacy CANopen sensors to higher-layer protocols; UARTs handle RS-485 Modbus and Ethernet MAC layer handshaking. Use Value: On-chip 4kB SRAM stores protocol stacks and message buffers - eliminates external RAM and reduces BOM cost and board area. |
| Medical Infusion Pump | Agricultural Telematics Node |
Use Scenario: Precise motor control, pressure sensing, and alarm management in battery-powered infusion pumps. IC Role / Device Role / Timing Role: Safety-critical controller running fail-safe state machine; uses SIESTA CAN mode to minimize current draw during standby. Use Value: Stop-mode current of 1µA (typical) extends battery life; dual CAN enables redundant communication with pump head and display modules. |
Use Scenario: GPS-enabled tractor telemetry unit collecting engine diagnostics, implement status, and soil sensor data. IC Role / Device Role / Timing Role: Edge node aggregating J1939 CAN bus data from engine ECU and ISOBUS CAN from implements; logs to SD card via SPI. Use Value: Hardware math accelerator computes fuel efficiency metrics in real time; -40°C to +85°C rating ensures operation in unheated cab environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed 8051-based microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS80C400 | Enhanced successor with 64kB on-chip flash, Ethernet MAC, and USB; same pinout but requires different boot configuration. | Replaces DS80C390-QNR where firmware updates in field or network connectivity are required. | Select DS80C400 only if flash storage, Ethernet, or USB are mandatory - not a drop-in replacement due to boot ROM differences. |
| ST7FLITE09Y0M6 | 8-bit ST7 core (not 8051-compatible); 32kB flash, single CAN 2.0B, 10-bit ADC; 64-pin LQFP package. | Suitable for cost-sensitive CAN nodes where 8051 code reuse is unnecessary and analog integration is preferred. | Choose ST7FLITE09Y0M6 when migrating legacy designs is not required and integrated ADC/peripherals reduce system component count. |
Compared with DS80C390-QNR, DS80C400 adds Ethernet and flash but increases complexity and cost; ST7FLITE09Y0M6 offers lower system cost and integrated analog but sacrifices 8051 code compatibility and dual CAN capability - making DS80C390-QNR optimal for maintaining legacy firmware while requiring dual-bus CAN robustness.
Availability
DS80C390-QNR is available at Aetrix Electronics and suitable for industrial motion control, factory automation gateways, medical infusion pumps, and agricultural telematics requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for DS80C390-QNR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (acquired by Analog Devices in 2021) designs precision analog and mixed-signal ICs for industrial, medical, and communications applications - emphasizing reliability, low power, and high integration.
The DS80C390-QNR belongs to Maxim's high-speed microcontroller product line, engineered specifically for deterministic real-time control in harsh environments where dual CAN 2.0B, wide temperature operation, and 8051 software compatibility are essential.
FAQ
What is the maximum crystal frequency supported by the DS80C390-QNR?
The DS80C390-QNR supports a maximum crystal frequency of 40MHz. This enables an effective instruction execution rate of approximately 100MHz due to its 4-clock-per-machine-cycle architecture - three times faster than standard 8051 cores at the same crystal speed. The device also includes an optional internal frequency multiplier to achieve full-speed operation with lower-frequency crystals, reducing electromagnetic interference.
Does the DS80C390-QNR include on-chip flash or ROM memory?
No, the DS80C390-QNR does not include on-chip flash or ROM. It features 4kB of internal SRAM that can be used as program memory, data memory, or stack space - but external program memory must be connected since the EA pin must be tied to GND. Code execution occurs from external memory mapped via the 22-bit address bus, with support for multiplexed or nonmultiplexed interfaces.
How many CAN controllers does the DS80C390-QNR integrate, and what protocol versions do they support?
The DS80C390-QNR integrates two independent full-function CAN 2.0B controllers. Each supports both standard 11-bit and extended 29-bit identifier formats, 15 configurable message objects, and higher-layer protocols including DeviceNet™ and SDS. They operate autonomously with SIESTA low-power mode and disable transmitter functionality during autobaud detection - ensuring robust interoperability in industrial CAN networks.
What package type and temperature range does the DS80C390-QNR use?
The DS80C390-QNR is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC) and is rated for operation from -40°C to +85°C. This industrial temperature range, combined with the PLCC's mechanical stability and thermal performance, makes it suitable for deployment in demanding environments such as factory floors, agricultural equipment, and medical devices without additional thermal management.
Can the DS80C390-QNR operate with a nonmultiplexed address/data bus?
Yes, the DS80C390-QNR supports both multiplexed and nonmultiplexed memory interfaces. The MUX pin selects the mode: when low, Port 0 serves as multiplexed AD0–AD7 with ALE strobing; when high, Port 0 becomes a dedicated bidirectional data bus while Port 1 provides A0–A7. This flexibility allows seamless migration from legacy 8051 designs and simplifies external memory interfacing in new implementations.
DS80C390-QNR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package/Case:
- 68-LCC (J-Lead)
- Series:
- 80C
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 40MHz
- Connectivity:
- CANbus, EBI/EMI, SIO, UART/USART
- Peripherals:
- Power-Fail Reset, WDT
- Number of I/O:
- 32
- Program Memory Size:
- -
- Program Memory Type:
- ROMless
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 3.85V ~ 5.5V
- Data Converters:
- -
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
DS80C390-QNR FAQ
1.How can I place an order for DS80C390-QNR through Aetrix?
Please submit a Request for Quotation (RFQ) for DS80C390-QNR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS80C390-QNR reliable?
The price and inventory of DS80C390-QNR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS80C390-QNR is usually 5 days.
3.What payment methods are accepted for DS80C390-QNR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS80C390-QNR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS80C390-QNR?
DS80C390-QNR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS80C390-QNR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS80C390-QNR?
For technical support, including DS80C390-QNR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS80C390-QNR requirements.
6.How does Aetrix verify that DS80C390-QNR is sourced from the original manufacturer or authorized distributors?
All DS80C390-QNR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS80C390-QNR meets industry standards.
7.What is the process for return or replacement of DS80C390-QNR?
All DS80C390-QNR units undergo pre-shipment inspection (PSI). If there is an issue with DS80C390-QNR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS80C390-QNR part is unused and in its original packaging.
Return procedure for DS80C390-QNR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS80C390-QNR Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
