Analog Devices Inc./Maxim Integrated DS8500-JND+

Overview

DS8500-JND+ from Maxim Integrated is a single-chip, half-duplex HART modem IC designed for overlaying 1200bps FSK digital communication onto 4mA–20mA current loops. It integrates ADC, digital filter/demodulator, DAC, and carrier detect (OCD), operates from 2.7V to 3.6V, consumes ≤285μA active current, and uses a standard 3.6864MHz crystal. It is certified by the HART Communication Foundation (Certificate L2-06-1000-346) and targets low-power process transmitters.

For engineers reviewing the DS8500-JND+ datasheet, DS8500-JND+ pinout, DS8500-JND+ application, or DS8500-JND+ equivalent, key selection considerations include its HART registration status, 20-pin TQFN-EP package with exposed pad, dual-mode RTS-controlled operation (modulator/demodulator), internal 1.23V reference output, and phase-continuous 1200Hz/2200Hz FSK generation compliant with IEC 61000-4-4/6 immunity requirements in noisy industrial environments.

Technical Context

The DS8500-JND+ implements a fully integrated analog front-end and digital signal processing path: an on-chip ADC digitizes the FSK_IN signal after external RC filtering, followed by a digital filter and demodulator that recovers UART-formatted data at 1200bps; the modulator accepts D_IN UART input and drives FSK_OUT with phase-continuous sine-wave switching between 1200Hz (mark) and 2200Hz (space).

Operation is controlled via RTS (mode select), XCEN (external clock enable), and MODE (HART/legacy support); it features built-in power monitoring (RST reset threshold 2.64V), dual ground domains (AGND/DGND), and internal VREF output only during demodulation-disabled in modulator mode to reduce power consumption.

Key Specifications

Pinout & Package

DS8500-JND+ is housed in a space-saving 5mm × 5mm × 0.8mm, 20-pin Thin Quad Flat No-lead (TQFN-EP) package with exposed thermal pad (EP) requiring connection to AGND/DGND for optimal thermal performance and noise immunity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar HART physical layer modem applications.

Compared with AD5700-1ACPZ-RL7 and TI's TIDA-010007, the DS8500-JND+ offers lowest component count, smallest footprint (5mm × 5mm), and pre-certified HART compliance-making it optimal for volume production of standardized loop-powered transmitters where time-to-market and qualification cost are critical.

Availability

DS8500-JND+ is available at Aetrix Electronics and suitable for 4mA–20mA loop-powered transmitters, HART multiplexers, and industrial field instrumentation requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for DS8500-JND+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a semiconductor company specializing in precision analog, mixed-signal, and high-reliability ICs for industrial, medical, and communications markets.

The DS8500-JND+ belongs to Maxim's industrial communications product line, engineered specifically to simplify HART physical layer implementation in resource-constrained, loop-powered field devices while ensuring full protocol conformance and certification.

FAQ

What is the HART certification status of the DS8500-JND+?

The DS8500-JND+ holds a valid HART Modem IC Registration Certificate (L2-06-1000-346) issued by the HART Communication Foundation. This certification confirms full compliance with the HART physical layer specification, including FSK frequency accuracy, output amplitude, and noise immunity. The DS8500-JND+ is tested per HCF test plan and qualifies as a registered modem IC-enabling OEMs to leverage this certification for faster end-product registration.

Does the DS8500-JND+ require external passive components for basic operation?

Yes-the DS8500-JND+ requires a 3.6864MHz crystal (or external clock source), a 0.1µF capacitor on the REF pin (when in demodulator mode), and a simple RC filter network (e.g., R1/R2/C2/C3) on FSK_IN for highpass/lowpass conditioning. No external op-amps, filters, or clock buffers are needed. The DS8500-JND+ integrates all core signal processing functions, minimizing external BOM to fewer than five passive components.

How does the DS8500-JND+ manage power in half-duplex operation?

The DS8500-JND+ disables receive circuits during transmit and vice versa, achieving ≤285μA active current. Power gating is automatic and synchronized with RTS-driven mode transitions: in modulator mode, the ADC, digital filter, and OCD blocks are powered down; in demodulator mode, the DAC and FSK_OUT driver are disabled. The internal 1.23V reference is also powered down during modulation to further reduce quiescent draw.

Can the DS8500-JND+ operate with a clock other than 3.6864MHz?

No-the DS8500-JND+ is designed exclusively for 3.6864MHz clock input (±1%) to generate precisely timed 1200Hz and 2200Hz FSK symbols. Deviations outside this tolerance cause bit timing errors and violate HART physical layer compliance. The device accepts either a crystal across XTAL1/XTAL2 or an external CMOS clock at XTAL1 when XCEN = high; both sources must be 3.6864MHz ±1%.

What is the function of the MODE pin on the DS8500-JND+?

The MODE pin on the DS8500-JND+ selects operational compatibility: tied high, it configures the device for full HART protocol compliance (default); tied low, it enables legacy support for older non-HART systems that require alternate timing or signal levels. This pin does not affect FSK frequency or UART format-it modifies internal state machine behavior for backward compatibility only. For new HART designs, MODE must be connected to DVDD.