Analog Devices Inc./Maxim Integrated DS87C520-QNL/T&R
- Part No.:
- DS87C520-QNL/T&R
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Microcontrollers
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
DS87C520-QNL/T&R.pdf
- Description:
- IC MCU 8BIT 16KB OTP 44PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS87C520-QNL/T&R from Maxim Integrated is a high-speed, 8051-compatible microcontroller with 16kB on-chip EPROM, 1kB MOVX-accessible SRAM, 256 bytes of scratchpad RAM, three 16-bit timer/counters, and dual full-duplex serial ports. It operates at up to 33MHz (121ns single-cycle instruction), supports -40°C to +85°C industrial temperature range, and is packaged in 44-pin PLCC for embedded control in instrumentation and industrial automation.
For engineers reviewing the DS87C520-QNL/T&R datasheet, DS87C520-QNL/T&R pinout, DS87C520-QNL/T&R application, or DS87C520-QNL/T&R equivalent, key selection considerations include its 4-clock-per-machine-cycle architecture, ROMSIZE register for dynamic internal/external memory mapping, Power Management Mode (PMM) for low-power operation, EMI reduction via ALE disable, and dual data pointer support for accelerated block memory transfers.
Technical Context
The DS87C520-QNL/T&R implements a redesigned 8051 core executing instructions in 4 clocks per machine cycle-three times faster than standard 8051 at identical crystal frequency-while maintaining full 8051 instruction set and pin compatibility. Its memory subsystem includes configurable ROMSIZE (0–16kB) and software-selectable on-chip 1kB SRAM accessed via MOVX.
Hardware features include two independent serial ports (UART0 and UART1), programmable Watchdog Timer, Power-Fail Reset with early-warning interrupt, Brownout Monitor, and Power Management Mode enabling CPU clock division by 64 or 1024 for ultra-low-power operation. The device uses dual DPTRs and stretchable MOVX cycles (2–9 machine cycles) to interface flexibly with fast or slow external peripherals without glue logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 8051-compatible, 4-clock-per-machine-cycle execution (vs. 12 in legacy 8051) |
| Max Clock Frequency | 33MHz crystal input, enabling 82.5MHz apparent instruction throughput |
| On-Chip Memory | 16kB EPROM program memory + 1kB MOVX-accessible SRAM + 256B direct RAM |
| Timer/Counter Resources | Three 16-bit timers/counters, with optional 4- or 12-clock-per-increment modes |
| Serial Interfaces | Two independent full-duplex UARTs (UART0 on P3.0/P3.1, UART1 on P1.2/P1.3) |
| Power Management | Programmable clock divider (×64 or ×1024) reducing CPU speed to 187.5kHz or 11.7kHz at 12MHz crystal |
| EMI Reduction | Software-controllable ALE disable (PMR.2 = 1) to suppress address latch pulses when unused |
Pinout & Package
DS87C520-QNL/T&R is housed in a 44-pin Plastic Leaded Chip Carrier (PLCC) package with gull-wing leads, rated for -40°C to +85°C operation and RoHS-compliant (lead-free).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P1.2 / P1.3 | UART1 RX/TX | Second hardware serial port I/O, freeing P3.0/P3.1 for other functions or enabling dual asynchronous communication |
| P1.4–P1.7 | INT2–INT5 | Four additional edge-triggered external interrupts beyond standard INT0/INT1, supporting complex event-driven firmware |
| EA | External Access Input | Active-low signal selecting internal ROM (EA = VCC) or forcing external program fetch (EA = GND), overriding ROMSIZE register |
| ALE | Address Latch Enable | Output strobe for latching Port 0 LSB during external memory access; can be disabled via PMR.2 to reduce EMI |
| ROMSIZE[2:0] | SFR bits RMS2–RMS0 (C2h) | Software-configurable register selecting effective internal ROM size (0–16kB) to enable boot-from-external-Flash or memory-mapped peripheral overlay |
Key Features
| Feature | Design Value |
|---|---|
| Dual Data Pointer (DPTR0/DPTR1) | Eliminates repeated DPTR reloads during block memory moves, accelerating MOVX-based data transfers by up to 50% |
| Stretchable MOVX Timing | Configurable 2–9 machine-cycle read/write strobes (CKCON.2–0) enabling reliable interfacing with slow peripherals like LCD controllers or legacy RAM |
| ROMSIZE Register | Dynamic on-the-fly adjustment of internal ROM boundary (0–16kB) allows seamless switching between internal firmware and external Flash boot code |
| Power Management Mode (PMM) | Reduces active power consumption by >90% at lowest clock division setting, extending battery life in portable instrumentation |
| Early-Warning Power-Fail Interrupt | Generates interrupt before brownout reset occurs, enabling safe state save and controlled shutdown of critical system resources |
Applications
| Industrial PLC I/O Module | Medical Diagnostic Instrument |
|---|---|
Use Scenario: Real-time acquisition and preprocessing of analog sensor data from multiple channels in a DIN-rail mounted controller. IC Role / Device Role / Timing Role: Primary MCU executing deterministic control loops, managing dual UARTs for Modbus RTU communication and local debug, and using stretchable MOVX to interface with slow ADC/DAC peripherals. Use Value: 4-clock core enables sub-100μs loop response at 33MHz; ROMSIZE allows field-upgradable firmware stored in external Flash while retaining secure boot from internal EPROM. | Use Scenario: Portable ultrasound front-end unit requiring low-power operation, precise timing for echo sampling, and dual serial links for host PC and display panel. IC Role / Device Role / Timing Role: Central controller handling time-critical pulse generation, ADC triggering, and buffered data streaming via UART0 (to host) and UART1 (to display), with watchdog supervision. Use Value: Power Management Mode extends battery runtime; dual DPTR accelerates waveform buffer transfers; early-warning power-fail interrupt preserves unsaved scan data before shutdown. |
| Automotive Body Control Unit | Smart Energy Meter |
Use Scenario: Consolidated lighting, door lock, and window control module operating across extended automotive temperature range. IC Role / Device Role / Timing Role: Robust MCU managing CAN gateway logic (via external transceiver), PWM dimming outputs, and discrete I/O monitoring with Brownout Monitor and Power-Fail Reset. Use Value: -40°C to +85°C rating ensures reliability; 16kB EPROM stores complex vehicle-specific configuration; dual UARTs support diagnostic logging and calibration over separate channels. | Use Scenario: Revenue-grade electricity meter with tamper detection, real-time clock, and RS-485 communication for utility grid integration. IC Role / Device Role / Timing Role: Main processor executing metrology algorithms, managing secure EEPROM writes, and driving isolated RS-485 transceiver via UART0 while UART1 handles IR optical port. Use Value: On-chip 1kB SRAM buffers metering samples without external memory; ROMSIZE enables secure bootloader partitioning; programmable watchdog prevents firmware lockup during long-term deployment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS87C520-MNL/T&R | Same core, memory, and peripherals; differs only in 40-pin PDIP package (vs. 44-pin PLCC) | Requires PCB redesign due to different pin count, footprint, and I/O mapping (e.g., no P1.4–P1.7 on PDIP) | Select DS87C520-MNL/T&R only if legacy through-hole assembly or space-constrained layout favors DIP over PLCC. |
| DS83C520-QNL/T&R | Mask ROM version (not EPROM); identical pinout, speed, and feature set except non-reprogrammable program memory | Used in high-volume cost-sensitive production where firmware is fixed and field updates are unnecessary | Choose DS83C520-QNL/T&R for final production runs with verified firmware; retain DS87C520-QNL/T&R for prototyping and firmware development. |
Compared with DS87C520-MNL/T&R, DS87C520-QNL/T&R offers higher I/O density and access to all 13 interrupts including INT2–INT5, while DS83C520-QNL/T&R trades EPROM reprogrammability for lower unit cost and enhanced security against firmware extraction.
Availability
DS87C520-QNL/T&R is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, automotive body electronics, and smart energy metering requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for DS87C520-QNL/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and high-reliability semiconductor solutions for industrial, medical, and automotive markets.
The DS87C520-QNL/T&R belongs to Maxim's high-speed 8051-compatible microcontroller family, engineered to deliver deterministic real-time performance, robust power management, and flexible memory expansion for resource-constrained embedded systems.
FAQ
What is the maximum operating frequency of the DS87C520-QNL/T&R?
The DS87C520-QNL/T&R supports a maximum crystal frequency of 33MHz, delivering a peak instruction execution rate of approximately 82.5MHz due to its 4-clock-per-machine-cycle architecture. At this speed, the fastest single-cycle instruction completes in 121ns. The device maintains full functionality across its specified -40°C to +85°C industrial temperature range when operated within recommended voltage and decoupling guidelines.
How does the ROMSIZE feature work in the DS87C520-QNL/T&R?
The ROMSIZE feature in the DS87C520-QNL/T&R is controlled by bits RMS2–RMS0 in SFR location C2h and dynamically selects the upper boundary of on-chip program memory (0–16kB). This allows the DS87C520-QNL/T&R to map external Flash into the 0000h–3FFFh address space while retaining internal EPROM for secure boot code. Changing ROMSIZE requires timed-access write sequence and must be performed from memory addresses valid both before and after the change to prevent execution errors.
Can the DS87C520-QNL/T&R operate in low-power mode, and how is it configured?
Yes, the DS87C520-QNL/T&R supports Power Management Mode (PMM) via the PMR register (C4h). Setting CD1/CD0 to 01b or 10b configures the CPU to run from crystal/64 or crystal/1024, reducing machine cycle rate to 187.5kHz or 11.7kHz at 12MHz crystal. PMM exits automatically on any interrupt or reset, and software retains full control over peripherals and I/O during reduced-speed operation-enabling significant power savings in battery-powered DS87C520-QNL/T&R applications.
What are the key differences between DS87C520-QNL/T&R and DS83C520-QNL/T&R?
The DS87C520-QNL/T&R contains 16kB of one-time-programmable EPROM, while the DS83C520-QNL/T&R uses factory-masked ROM with identical pinout, speed, peripherals, and SFRs. All functional features-including dual UARTs, Power Management Mode, ROMSIZE, and dual DPTR-are identical. The DS87C520-QNL/T&R is intended for development and low-volume production where firmware iteration is required; the DS83C520-QNL/T&R targets high-volume cost-sensitive deployments with finalized firmware.
Does the DS87C520-QNL/T&R support external memory expansion, and how is it implemented?
Yes, the DS87C520-QNL/T&R supports external memory expansion via multiplexed address/data bus on Port 0 (AD0–AD7) and high-order address on Port 2 (A8–A15), controlled by PSEN (for external ROM) and RD/WR (for external RAM). External access is enabled when EA = GND or when ROMSIZE limits internal decode range. MOVX instructions target external memory when DME1/DME0 bits (PMR.1/PMR.0) configure external-only data space or when addresses exceed 03FFh in internal-SRAM mode-providing full 64kB expandability compatible with standard 8051 systems.
DS87C520-QNL/T&R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package/Case:
- 44-LCC (J-Lead)
- Series:
- 87C
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Verified
- Core Processor:
- 8051
- Core Size:
- 8-Bit
- Speed:
- 33MHz
- Connectivity:
- EBI/EMI, SIO, UART/USART
- Peripherals:
- Power-Fail Reset, WDT
- Number of I/O:
- 32
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- OTP
- EEPROM Size:
- -
- RAM Size:
- 1K x 8
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 5.5V
- Data Converters:
- -
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
DS87C520-QNL/T&R FAQ
1.How can I place an order for DS87C520-QNL/T&R through Aetrix?
Please submit a Request for Quotation (RFQ) for DS87C520-QNL/T&R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS87C520-QNL/T&R reliable?
The price and inventory of DS87C520-QNL/T&R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS87C520-QNL/T&R is usually 5 days.
3.What payment methods are accepted for DS87C520-QNL/T&R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS87C520-QNL/T&R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS87C520-QNL/T&R?
DS87C520-QNL/T&R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS87C520-QNL/T&R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS87C520-QNL/T&R?
For technical support, including DS87C520-QNL/T&R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS87C520-QNL/T&R requirements.
6.How does Aetrix verify that DS87C520-QNL/T&R is sourced from the original manufacturer or authorized distributors?
All DS87C520-QNL/T&R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS87C520-QNL/T&R meets industry standards.
7.What is the process for return or replacement of DS87C520-QNL/T&R?
All DS87C520-QNL/T&R units undergo pre-shipment inspection (PSI). If there is an issue with DS87C520-QNL/T&R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS87C520-QNL/T&R part is unused and in its original packaging.
Return procedure for DS87C520-QNL/T&R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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