Texas Instruments DS90C124QVS/NOPB

Overview

DS90C124QVS/NOPB from Texas Instruments is a 24-bit FPD-Link II deserializer IC that recovers embedded clock and converts LVDS serial data to parallel LVCMOS outputs. It operates from 5 MHz to 35 MHz, supports AC-coupled interconnects via DC-balanced encoding, and delivers 24-bit parallel output across three PTO-controlled LVCMOS groups with ±8-kV HBM ESD tolerance for automotive display interfaces.

For engineers reviewing the DS90C124QVS/NOPB datasheet, DS90C124QVS/NOPB pinout, DS90C124QVS/NOPB application, or DS90C124QVS/NOPB equivalent, key selection criteria include its 48-pin TQFP package, LOCK status flag, RCLK timing control with configurable edge, tri-state power-down (RPWDNB), and compliance with AEC-Q100 Grade 2 (–40°C to 105°C).

Technical Context

The DS90C124QVS/NOPB implements a CDR-based receiver architecture with integrated PLL for clock recovery from the incoming LVDS stream, eliminating need for external reference clocks. It decodes DC-balanced data, supports live-pluggable operation via RDL coding, and provides balanced setup/hold timing between RCLK and ROUT signals.

Its parallel interface is segmented into three PTO-enabled LVCMOS output groups (ROUT[7:0], [15:8], [23:16]) with independent slew control to minimize SSO effects. Configuration pins RRFB and RPWDNB enable falling/rising edge sampling and hardware-controlled power-down, respectively.

Key Specifications

Pinout & Package

DS90C124QVS/NOPB uses a 48-pin TQFP package (7.00 mm × 7.00 mm) with exposed thermal pad. Pin functions are fully defined per TI SNLS209M datasheet Rev M (Jan 2017), including dedicated analog/digital power and ground separation for noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar deserializer applications.

Compared with DS90C124QVS/NOPB, DS90UB925QSQ/NOPB enables higher resolution and diagnostic capability at cost of increased complexity, while MAX9271GTJ/V+T trades protocol compatibility for alternate automotive serialization infrastructure-neither is pin-compatible, and both require PCB and firmware rework.

Availability

DS90C124QVS/NOPB is available at Aetrix Electronics and suitable for automotive central information displays, instrument cluster displays, and heads-up displays requiring stable component supply across extended temperature and long-lifecycle programs.

Supply support for DS90C124QVS/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and automotive ICs with broad design-in support and automotive qualification expertise.

The DS90C124QVS/NOPB belongs to TI's FPD-Link II serializer/deserializer product line, engineered specifically for high-reliability, low-EMI video transport in automotive cockpit displays and driver-assistance systems.

FAQ

What is the primary function of the DS90C124QVS/NOPB in an automotive display system?

The DS90C124QVS/NOPB serves as a deserializer that recovers clock and data from an incoming FPD-Link II LVDS stream and outputs synchronized 24-bit parallel LVCMOS video data. It enables compact, low-noise video transmission over shielded twisted-pair cables in automotive central displays, instrument clusters, and HUDs-replacing bulky parallel interfaces while maintaining timing integrity via its LOCK flag and balanced RCLK-to-ROUT timing.

Does the DS90C124QVS/NOPB require an external reference clock?

No, the DS90C124QVS/NOPB does not require an external reference clock. It incorporates a built-in clock and data recovery (CDR) circuit with PLL that extracts timing directly from the embedded clock within the LVDS serial stream. This eliminates dependency on a separate clock source and simplifies system-level timing design-confirmed in the SNLS209M datasheet Section 3 and Figure 1.

How does the LOCK pin on the DS90C124QVS/NOPB improve system reliability?

The LOCK pin on the DS90C124QVS/NOPB is an active-high LVCMOS output that asserts only when the internal PLL achieves and maintains stable lock to the incoming serial data stream. This allows downstream logic-including display controllers and FPGA video pipelines-to gate data capture until valid synchronization is confirmed, preventing display artifacts or initialization failures during power-up or link reacquisition-explicitly documented in Pin Functions Table (page 5) and Section 8.3.

Can the DS90C124QVS/NOPB operate with AC-coupled LVDS inputs?

Yes, the DS90C124QVS/NOPB supports AC-coupled LVDS inputs via its internal DC-balanced decode engine. The device accepts RIN+/RIN− signals through external 100-nF AC-coupling capacitors (per datasheet Figure 5 and Pin Functions), enabling galvanic isolation and eliminating DC bias constraints on the interconnect-critical for long-harness automotive applications where ground potential differences exist.

What is the significance of the RPWDNB pin on the DS90C124QVS/NOPB?

The RPWDNB pin on the DS90C124QVS/NOPB is an active-high hardware control that places the deserializer into ultra-low-power sleep mode (50 µA typical). When RPWDNB is driven low, all parallel outputs (ROUT[23:0], RCLK, LOCK) enter tri-state, and the PLL is shut down-enabling rapid power cycling in display systems without full reinitialization. This behavior is specified in the Pin Functions table (page 5) and Electrical Characteristics (Section 6.5).