Texas Instruments DS90C185SQ/NOPB

Overview

DS90C185SQ/NOPB from Texas Instruments is a low-power 1.8-V LVCMOS-to-LVDS serializer for portable display interfaces, supporting SXGA+ (1400×1050@60 Hz) resolution with 24-bit RGB + 3 control signals (HS/VS/DE), 25–105 MHz pixel clock range, and 4D+C (4 data lanes + clock) FPD-Link output. It serves as the GPU-side transmitter in compact LCD modules for media tablets and netbooks.

For engineers reviewing the DS90C185SQ/NOPB datasheet, DS90C185SQ/NOPB pinout, DS90C185SQ/NOPB application, or DS90C185SQ/NOPB equivalent, key selection criteria include 1.8-V single-supply operation, 24-/18-bit RGB mode configurability via 18B_MODE, LVDS VOD select (±180 mV / ±300 mV), sleep-mode power-down (PDB), and WQFN-48 package compatibility with high-density portable layouts.

Technical Context

The DS90C185SQ/NOPB implements a parallel-to-serial conversion architecture with integrated PLL, accepting 28-bit LVCMOS inputs (24 RGB + 3 video control + 1 GP/L-R) and serializing them into four differential LVDS data lanes (TxOUT0–3) plus TxCLKOUT. Its dual-mode operation-24-bit (4D+C) or 18-bit (3D+C)-is controlled by the 18B_MODE pin, which tri-states TxOUT3 in 18-bit mode to reduce power.

Timing is synchronized to an external pixel clock (25–105 MHz); data latching edge (rising/falling) is configurable via RFB pin. The serializer supports spread-spectrum clocking and achieves ≤0.035 UI cycle-to-cycle jitter at 105 MHz, with propagation delay of 10.54–13.96 ns and channel-to-channel skew ≤110 ps.

Key Specifications

Pinout & Package

DS90C185SQ/NOPB uses a 48-pin WQFN package (TI package code NJV) with 0.4-mm pitch and thermally enhanced DAP (die attach pad) connected to GND. Pinout includes 28 LVCMOS inputs (D0–D27), 10 LVDS outputs (TxOUT0–3±, TxCLKOUT±), 5 control inputs (RFB, 18B_MODE, VOD_SEL, PDB, CLK), and 5 power/ground terminals (VDD, VDDTX, VDDPLL, GND×2).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90C187SQ/NOPB, DS90C185SQ/NOPB provides identical core serialization and power features at lower cost and reduced configuration overhead; versus SN65LVDS31IPW, it integrates full parallel-to-serial conversion and 1.8-V operation-eliminating external logic and voltage translation in modern portable designs.

Availability

DS90C185SQ/NOPB is available at Aetrix Electronics and suitable for media tablet displays, netbook main screens, and portable monitor control boards requiring stable component supply, RoHS-compliant packaging, and long-term industrial availability.

Supply support for DS90C185SQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and consumer applications.

The DS90C185SQ/NOPB belongs to TI's FPD-Link serializer product line, engineered specifically for low-power, high-resolution display interfaces in portable electronics where size, thermal performance, and single-supply simplicity are critical.

FAQ

What is the primary function of the DS90C185SQ/NOPB in a display system?

The DS90C185SQ/NOPB functions as an LVCMOS-to-LVDS serializer that converts a 28-bit parallel video interface (24-bit RGB + HSync/VSync/DE) into a 4D+C (four data lanes + clock) FPD-Link LVDS stream. It sits between the GPU and display TCON, enabling high-speed, low-noise, low-power transmission over compact flex cables in portable devices. DS90C185SQ/NOPB supports both 24-bit and 18-bit RGB modes with hardware-configurable pins.

Does DS90C185SQ/NOPB support both 24-bit and 18-bit RGB color depths?

Yes, DS90C185SQ/NOPB supports both 24-bit RGB (4D+C mode) and 18-bit RGB (3D+C mode) via the 18B_MODE pin. When 18B_MODE = 0, all four LVDS data lanes operate; when 18B_MODE = 1, TxOUT3± is tri-stated and corresponding inputs are ignored, reducing power consumption by ~25%. DS90C185SQ/NOPB maintains identical pinout and timing behavior in both modes.

How does the PDB pin affect power consumption in DS90C185SQ/NOPB?

The PDB (Power Down Bar) pin places DS90C185SQ/NOPB into a low-power sleep state when driven LOW, reducing supply current to ≤200 µA. In this mode, the PLL shuts down, LVDS drivers are powered off and pulled to GND via 100-Ω resistors, and all outputs become high-impedance. DS90C185SQ/NOPB resumes full operation within 100 ns after PDB is asserted HIGH.

What LVDS load impedance does DS90C185SQ/NOPB require?

DS90C185SQ/NOPB requires a nominal 100-Ω differential load on each LVDS output pair (TxOUT0–3± and TxCLKOUT±), with acceptable range of 80–120 Ω. This matches ANSI/TIA/EIA-644-A LVDS receiver specifications and ensures signal integrity, proper common-mode rejection, and minimal reflections. Termination must be placed at the display-side receiver end.

Can DS90C185SQ/NOPB operate with a 25-MHz pixel clock for VGA resolution?

Yes, DS90C185SQ/NOPB supports pixel clock frequencies from 25 MHz to 105 MHz, making it fully compatible with VGA (640×480@60 Hz, ~25.2 MHz) and higher resolutions including SXGA+ (1400×1050@60 Hz, ~105 MHz). At 25 MHz, DS90C185SQ/NOPB delivers 700 Mbps total throughput (28 bits × 25 MHz) while maintaining sub-110-ps channel skew and <0.035 UI jitter.