Texas Instruments DS90C185SQX/NOPB

Overview

DS90C185SQX/NOPB from Texas Instruments is a low-power 1.8V LVDS serializer for portable display interfaces, converting 28-bit LVCMOS video (24-bit RGB + HSync/VSynch/DE + GPO) into FPD-Link 4D+C LVDS output. It supports SXGA+ (1400×1050@60Hz), operates from 25–105 MHz pixel clock, delivers 2.94 Gbps max throughput, and features sleep mode, spread-spectrum clock compatibility, and VOD-selectable LVDS drivers. It is used in media tablets and netbooks to replace bulky parallel RGB traces with compact differential pairs.

For engineers reviewing the DS90C185SQX/NOPB datasheet, DS90C185SQX/NOPB pinout, DS90C185SQX/NOPB application, or DS90C185SQX/NOPB equivalent, key selection criteria include 24/18-bit RGB mode configurability, 1.8V single-supply operation, WQFN-48 thermal performance, LVDS output compliance per ANSI/TIA/EIA-644–A, and power-down behavior under PDB control.

Technical Context

The DS90C185SQX/NOPB implements a parallel-to-LVDS serialization pipeline with integrated PLL, accepting 28 LVCMOS inputs at up to 105 MHz and generating four LVDS data lanes plus one LVDS clock lane (4D+C). Its internal architecture includes edge-selectable latching (via RFB pin), programmable VOD (±180 mV or ±300 mV), and tri-state control of TxOUT3 in 18-bit mode.

It supports two deterministic operating modes: 24-bit RGB (4D+C, all four TxOUT channels active) and 18-bit RGB (3D+C, TxOUT3 disabled), with independent power management via PDB (sleep mode draws ≤200 µA) and VOD_SEL (reduced swing lowers power by ~20% at 75 MHz). The device requires no external reference clock and locks to the incoming pixel clock.

Key Specifications

Pinout & Package

The DS90C185SQX/NOPB is housed in a thermally enhanced 6 mm × 6 mm × 0.8 mm WQFN-48 package with exposed thermal pad (DAP = GND). Pin pitch is 0.5 mm; RoHS-compliant, green (halogen-free) finish; MSL Level-1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90C187SQX/NOPB, DS90C185SQX/NOPB offers lower cost and proven qualification for portable battery life but limits max resolution to SXGA+. Versus SN65LVDS93IPWPR, it provides superior power efficiency, flexible voltage operation, and advanced power management-critical for mobile designs.

Availability

DS90C185SQX/NOPB is available at Aetrix Electronics and suitable for media tablets, netbooks, and portable medical monitors requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for DS90C185SQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS90C185SQX/NOPB belongs to TI's FPD-Link serializer family, engineered specifically for low-power, high-resolution display interfaces in portable consumer and industrial electronics.

FAQ

What is the maximum supported resolution and refresh rate for DS90C185SQX/NOPB?

The DS90C185SQX/NOPB supports up to SXGA+ resolution (1400×1050) at 60 Hz with 24-bit color depth. This is achieved using its full 28-bit LVCMOS input bus (24 RGB + 3 control + 1 GP) and 4D+C LVDS output at 105 MHz pixel clock, delivering 2.94 Gbps total throughput. Lower resolutions such as WXGA or XGA are also fully supported across the 25–105 MHz clock range.

Does DS90C185SQX/NOPB require an external reference clock?

No, DS90C185SQX/NOPB does not require an external reference clock. It uses the incoming LVCMOS pixel clock (CLK) as both timing reference and PLL input. The internal PLL locks directly to this clock, eliminating the need for crystal oscillators or clock generators. This simplifies layout and reduces BOM cost while maintaining tight skew control across LVDS outputs.

How does the PDB pin affect DS90C185SQX/NOPB operation?

The PDB (Power Down Bar) pin is an active-high control that places DS90C185SQX/NOPB into ultra-low-power sleep mode when driven LOW. In sleep mode, the PLL shuts down, LVDS drivers power off and terminate to GND via 100 Ω resistors, and supply current drops to ≤200 µA. The device retains pin configuration state and resumes normal operation within 100 ns after PDB is asserted HIGH.

Can DS90C185SQX/NOPB drive standard LVDS receivers compliant with ANSI/TIA/EIA-644–A?

Yes, DS90C185SQX/NOPB LVDS outputs comply fully with ANSI/TIA/EIA-644–A. Its differential output voltage (VOD) is configurable between ±180 mV and ±300 mV, both within the standard's 250–450 mVpp specification range. Output offset voltage (VOS) is tightly controlled at 0.8–1.0 V, and common-mode noise rejection is ensured by matched rise/fall times (0.18–0.5 ns) and channel-to-channel skew <110 ps.

What is the function of the RFB pin on DS90C185SQX/NOPB?

The RFB (Rising/Falling Edge Bit) pin selects the clock edge used to latch LVCMOS video data. When RFB = LOW (default, pulled down), data is sampled on the falling edge of CLK; when RFB = HIGH, sampling occurs on the rising edge. This allows timing alignment flexibility with the source GPU or TCON, independent of the downstream deserializer's strobe polarity.