Texas Instruments DS90C189TWRTDTQ1

Overview

DS90C189TWRTDTQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive-qualified RGB-to-LVDS bridge IC that converts 24-bit 1.8-V LVCMOS video data into dual-channel FPD-Link-compatible LVDS streams. It operates in SISO mode up to 105 MHz or SIDO mode up to 185 MHz, supports QXGA (2048×1536) and WQXGA-class displays, and consumes only 150 mW typical at 185 MHz. It serves as a timing-critical interface between host GPUs and display timing controllers in camera monitor systems.

For engineers reviewing the DS90C189TWRTDTQ1 datasheet, DS90C189TWRTDTQ1 pinout, DS90C189TWRTDTQ1 application, or DS90C189TWRTDTQ1 equivalent, this page delivers verified electrical specs, validated LVDS output configurations (4D+C, 8D+2C), confirmed AEC-Q100 Grade 2 thermal range (–40°C to +105°C), and precise power-down behavior with <10 mW sleep current - all critical for automotive display subsystem design and layout validation.

Technical Context

The DS90C189TWRTDTQ1 implements a parallel-to-serial conversion architecture with integrated PLL and dual LVDS transmitters. Its MODE0 pin selects between SISO (single-pixel serialization) and SIDO (single-to-dual pixel conversion), directly determining clock division ratio, latency (2×TCIP+10.54 ns vs. 9×TCIP+4.19 ns), and LVDS channel count (1 vs. 2).

It features configurable VODSEL (±220 mV or ±340 mV differential swing), RFB-controlled input latch edge (rising/falling), and dedicated PDB-controlled sleep mode that disables PLL and pulls LVDS outputs to GND via 100-Ω resistors - enabling robust power management without external sequencing.

Key Specifications

Pinout & Package

DS90C189TWRTDTQ1 is housed in a thermally enhanced 64-pin VQFN package (9.0 mm × 9.0 mm × 0.9 mm) with exposed DAP grounded to PCB for optimal thermal dissipation in automotive modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar RGB-to-LVDS bridge applications.

Compared with DS90C185QRTDTQ1 and DS90UB947QRTDTQ1, DS90C189TWRTDTQ1 uniquely balances dual-lane LVDS bandwidth (5.18 Gbps), deterministic SIDO latency, and integrated 1.8-V power architecture - making it the only option qualified for QXGA/WQXGA automotive display bridges with single-supply simplicity.

Availability

DS90C189TWRTDTQ1 is available at Aetrix Electronics and suitable for camera monitor systems, automotive head units, and digital instrument clusters requiring stable component supply across extended automotive product lifecycles.

Supply support for DS90C189TWRTDTQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive-grade ICs with decades of automotive qualification expertise.

DS90C189TWRTDTQ1 belongs to TI's FPD-Link III automotive bridge portfolio, engineered specifically for high-reliability, low-latency RGB-to-LVDS conversion in safety-critical display subsystems.

FAQ

What is the maximum display resolution supported by DS90C189TWRTDTQ1?

DS90C189TWRTDTQ1 supports up to QXGA (2048×1536) at 60 Hz in SISO mode and WQXGA (2560×1600) at 60 Hz in SIDO mode, both at 24 bpp color depth. Resolution capability is determined by input pixel clock frequency: 105 MHz max in SISO (28 bits × 105 MHz = 2.94 Gbps) and 185 MHz max in SIDO (28 bits × 185 MHz = 5.18 Gbps). The DS90C189TWRTDTQ1 datasheet confirms these limits under Recommended Operating Conditions.

How does the MODE0 pin affect DS90C189TWRTDTQ1 operation?

The MODE0 pin configures DS90C189TWRTDTQ1 between two fixed hardware modes: logic low selects Single Pixel In/Single Pixel Out (SISO), enabling one LVDS channel (4D+C) up to 105 MHz; logic high selects Single Pixel In/Dual Pixel Out (SIDO), enabling two LVDS channels (8D+2C) up to 185 MHz. This pin directly controls internal clock division, LVDS driver enablement, and latency calculation - no register programming is required. DS90C189TWRTDTQ1 behavior is fully determined at power-up based on MODE0 state.

What happens to LVDS outputs during DS90C189TWRTDTQ1 sleep mode?

When DS90C189TWRTDTQ1 enters sleep mode via PDB = low, the PLL shuts down, LVDS drivers are powered off, and all LVDS outputs (OA_C+/−, OA_[3:0]+/−, OB_C+/−, OB_[3:0]+/−) are actively pulled to GND through internal 100-Ω resistors - not tri-stated. This prevents floating lines and ensures predictable termination during low-power states. DS90C189TWRTDTQ1 maintains this state until PDB is asserted high and PLL lock is re-established (~1 ms).

Is DS90C189TWRTDTQ1 compatible with FPD-Link III receivers like DS90UB947-Q1?

Yes, DS90C189TWRTDTQ1 generates standard ANSI/TIA/EIA-644-A-compliant LVDS signals and supports 8D+2C configurations explicitly referenced in its datasheet as compatible with FPD-Link III devices. Its output voltage swing (±220 mV or ±340 mV), channel skew (≤110 ps), and timing parameters align with DS90UB947-Q1 receiver specifications. DS90C189TWRTDTQ1 has been validated in TI reference designs with DS90UB947-Q1 for end-to-end FPD-Link III links.

Does DS90C189TWRTDTQ1 require external termination resistors?

Yes, DS90C189TWRTDTQ1 requires external 100-Ω differential termination resistors at the far end of each LVDS pair (e.g., OA_C+/−, OA_[3:0]+/−, OB_C+/−, OB_[3:0]+/−) as specified in Section 7.3 of the datasheet. Unused LVDS outputs must also be terminated near the DS90C189TWRTDTQ1 package - for example, if operating in SISO mode, OB_C+/− and OB_[3:0]+/− must be terminated locally to prevent reflections and EMI.