Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Interface > Specialized

Texas Instruments DS90C363BMTX/NOPB

Name: DS90C363BMTX/NOPB
Brand: Texas Instruments
SKU: DS90C363BMTX/NOPB
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: DS90C363BMTX/NOPB

Manufacturer:: Texas Instruments

Category:: Specialized

Package:: 48-TFSOP (0.240", 6.10mm Width)

Datasheet:: DS90C363BMTX/NOPB.pdf

Description:: IC INTERFACE SPECIALIZED 48TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:520

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

DS90C363BMTX/NOPB from Texas Instruments is a +3.3V programmable LVDS transmitter for 18-bit flat panel display (FPD) links, supporting 65 MHz clock input and delivering 455 Mbps per LVDS channel with 345 mV typical differential output swing. It converts 21-bit CMOS/TTL data (18 RGB + 3 control) into three LVDS data streams plus one LVDS clock stream, enabling high-speed, low-EMI video interface in LCD timing applications.

For engineers reviewing the DS90C363BMTX/NOPB datasheet, DS90C363BMTX/NOPB pinout, DS90C363BMTX/NOPB application, or DS90C363BMTX/NOPB equivalent, key selection criteria include strobe-edge programmability (rising/falling via R_FB), spread-spectrum clock support up to ±2.5% center spread, power-down mode consuming <37 μW, and compatibility with TIA/EIA-644 LVDS standard in a 48-pin TSSOP package.

Technical Context

The DS90C363BMTX/NOPB integrates a PLL with no external components required, locks to input clock frequencies from 18–68 MHz, and supports both rising- and falling-edge data strobing via the R_FB pin-tied to VCC for rising edge or GND/NC for falling edge. Its LVDS outputs meet TIA/EIA-644 specifications with 250–450 mV differential voltage and <1.4 ns transition times.

It features input clock detection that pulls all LVDS pairs low when TxCLKIN is missing and /PD is high, and supports robust input sequencing-clock/data may be applied before or after power-up without special startup sequence. Spread spectrum tracking operates at modulation frequencies ≤100 kHz with ±2.5% center or −5% down spread.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage	3.0–3.6 V - Enables direct integration with 3.3V system rails; not 5V tolerant.
Data Throughput	170 MB/s at 65 MHz - Sustains dual-pixel SXGA resolution with real-time pixel streaming.
Differential Output Swing	345 mV (typ) - Ensures robust noise margin and low EMI over FR-4 PCB traces and flexible cables.
Power Consumption	130 mW (typ) at 65 MHz grayscale - 40% lower than BiCMOS alternatives, reducing thermal load in display modules.
Power-Down Current	<37 μW (typ) - Enables zero-power standby during display blanking or sleep modes.
Set/Hold Times	TSTC ≥2.5 ns, THTC ≥0.5 ns - Guarantees reliable sampling of TTL-level RGB/control signals at 65 MHz.
LVDS Compliance	TIA/EIA-644 compliant - Ensures interoperability with standard LVDS receivers including DS90CF366.

Pinout & Package

DS90C363BMTX/NOPB is housed in a 48-pin TSSOP (DGG) package with 1.2 mm max height, JEDEC MO-153 compliant, and rated for −10°C to +70°C operating temperature. Pin 1 orientation follows Q1 quadrant in tape-and-reel packaging.

Pin/Terminal	Circuit Role	Design Meaning
TxIN[0:20]	21-bit TTL input bus	Accepts 6R+6G+6B+3 control (FPLINE/FPFRAME/DRDY); not 5V tolerant.
FPSHIFT IN (TxCLK IN)	Input clock	Falling-edge strobe by default; rising-edge selectable via R_FB configuration.
R_FB	Strobe mode select	Pull to VCC → rising-edge strobe; pull to GND or leave NC → falling-edge strobe.
TxOUT+[0:2], TxOUT−[0:2]	3× LVDS data pairs	Transmit 18-bit RGB + 3 control bits across three differential channels.
TxCLK OUT+, TxCLK OUT−	LVDS clock pair	Carries synchronized transmit clock; enables receiver clock recovery without separate reference.
PWR DOWN	Active-low enable	Tri-states all LVDS outputs and reduces supply current to <37 μW when asserted.
VCC, PLL VCC, LVDS VCC	Separate power domains	Independent 3.3V supplies for TTL inputs, PLL core, and LVDS drivers-enabling optimized decoupling.
GND, PLL GND, LVDS GND	Ground domains	Three isolated ground returns minimize crosstalk between logic, PLL, and analog output sections.

Key Features

Feature	Design Value
Programmable strobe edge	Selectable rising/falling data capture via R_FB pin-enables interoperability with both DS90CF366 (falling) and rising-edge receivers without translation logic.
Spread spectrum clock support	Tracks SSCG inputs up to 100 kHz modulation with ±2.5% center or −5% down spread-reduces EMI peak emissions in display subsystems.
Input clock detection	Automatically forces LVDS outputs low when TxCLKIN is absent and /PD is high-prevents undefined video output during clock loss.
No external PLL components	Integrated PLL eliminates external capacitors/resistors-reducing BOM count and layout area in space-constrained display timing boards.
Robust input sequencing	Allows clock/data application before or after power-up, and supports dynamic video mode changes without mandatory /PD cycling-simplifying graphics controller integration.

Applications

Industrial LCD Timing Interface	Embedded Medical Display Module
Use Scenario: Driving 1080p monochrome LCD panels in factory automation HMIs where cable EMI must comply with CISPR 22 Class B limits. IC Role / Device Role / Timing Role: Converts parallel RGB+control signals from an ARM-based SoC into serialized LVDS streams synchronized to a 65 MHz pixel clock. Use Value: 345 mV LVDS swing and 455 Mbps/channel throughput ensure signal integrity over 30 cm flex cables; 40% lower power vs. BiCMOS alternatives extends thermal headroom in sealed enclosures.	Use Scenario: Interfacing FPGA-based video processors to high-resolution diagnostic displays in portable ultrasound equipment. IC Role / Device Role / Timing Role: Acts as FPD-Link transmitter bridging 21-bit parallel video bus to LVDS physical layer, supporting dual-pixel SXGA timing with embedded DRDY handshake. Use Value: Input clock detection prevents spurious display artifacts during probe reconnection; <37 μW power-down mode enables instant-on capability with battery runtime preservation.
Avionics Cabin Display System	Automotive Infotainment Head Unit
Use Scenario: Transmitting video from a safety-critical graphics controller to cockpit multi-function displays requiring DO-160E lightning-induced transient immunity. IC Role / Device Role / Timing Role: Provides galvanically isolated LVDS transmission path with controlled slew rates (<1.4 ns transitions) and 3.3V operation compatible with aircraft avionics power architecture. Use Value: Spread spectrum clock support reduces narrowband EMI peaks by >10 dB, easing compliance with DO-160E Section 20 radiated emissions requirements.	Use Scenario: Connecting infotainment SoC to TFT-LCD cluster display in vehicles operating across −40°C to +105°C ambient (with local thermal management). IC Role / Device Role / Timing Role: Translates 18-bit RGB and FPFRAME/FPLINE timing signals into LVDS format for long-reach, noise-immune interconnect within dashboard assemblies. Use Value: Best-in-class set/hold times (TSTC ≥2.5 ns) guarantee reliable sampling of fast-switching automotive graphics data; TSSOP package enables automated optical inspection (AOI) on production lines.

Industrial LCD Timing Interface

Embedded Medical Display Module

Use Scenario: Driving 1080p monochrome LCD panels in factory automation HMIs where cable EMI must comply with CISPR 22 Class B limits.

IC Role / Device Role / Timing Role: Converts parallel RGB+control signals from an ARM-based SoC into serialized LVDS streams synchronized to a 65 MHz pixel clock.

Use Value: 345 mV LVDS swing and 455 Mbps/channel throughput ensure signal integrity over 30 cm flex cables; 40% lower power vs. BiCMOS alternatives extends thermal headroom in sealed enclosures.

Use Scenario: Interfacing FPGA-based video processors to high-resolution diagnostic displays in portable ultrasound equipment.

IC Role / Device Role / Timing Role: Acts as FPD-Link transmitter bridging 21-bit parallel video bus to LVDS physical layer, supporting dual-pixel SXGA timing with embedded DRDY handshake.

Use Value: Input clock detection prevents spurious display artifacts during probe reconnection; <37 μW power-down mode enables instant-on capability with battery runtime preservation.

Avionics Cabin Display System

Automotive Infotainment Head Unit

Use Scenario: Transmitting video from a safety-critical graphics controller to cockpit multi-function displays requiring DO-160E lightning-induced transient immunity.

IC Role / Device Role / Timing Role: Provides galvanically isolated LVDS transmission path with controlled slew rates (<1.4 ns transitions) and 3.3V operation compatible with aircraft avionics power architecture.

Use Value: Spread spectrum clock support reduces narrowband EMI peaks by >10 dB, easing compliance with DO-160E Section 20 radiated emissions requirements.

Use Scenario: Connecting infotainment SoC to TFT-LCD cluster display in vehicles operating across −40°C to +105°C ambient (with local thermal management).

IC Role / Device Role / Timing Role: Translates 18-bit RGB and FPFRAME/FPLINE timing signals into LVDS format for long-reach, noise-immune interconnect within dashboard assemblies.

Use Value: Best-in-class set/hold times (TSTC ≥2.5 ns) guarantee reliable sampling of fast-switching automotive graphics data; TSSOP package enables automated optical inspection (AOI) on production lines.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS transmitter applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
DS90C363AMTX/NOPB	Predecessor version; lacks improved set/hold timing and spread spectrum clock support.	Not suitable for new designs requiring SSCG compliance or tighter timing margins at 65 MHz.	Select DS90C363BMTX/NOPB for full feature set and guaranteed performance at max clock rate.
SN75LVDS84DGGR	Fixed falling-edge strobe only; no R_FB programmability; higher 180 mW typical power at 65 MHz.	Requires matching falling-edge receiver; less flexible for mixed-legacy system upgrades.	Choose DS90C363BMTX/NOPB when strobe-edge flexibility, lower power, or SSCG are required.

Compared with DS90C363AMTX/NOPB and SN75LVDS84DGGR, DS90C363BMTX/NOPB delivers superior timing margins, integrated spread spectrum support, and programmable strobe edge-making it the optimal choice for new FPD-Link designs targeting EMI reduction, power efficiency, and interoperability across receiver variants.

Availability

DS90C363BMTX/NOPB is available at Aetrix Electronics and suitable for industrial HMI, medical imaging displays, avionics cabin systems, and automotive infotainment requiring stable component supply and long-term lifecycle assurance.

Supply support for DS90C363BMTX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions for display and industrial markets.

The DS90C363BMTX/NOPB belongs to TI's FPD-Link family, engineered specifically for low-EMI, high-bandwidth video transport in flat-panel display systems-from portable medical devices to aerospace-grade instrumentation.

FAQ

What is the maximum supported input clock frequency for DS90C363BMTX/NOPB?

The DS90C363BMTX/NOPB supports input clock frequencies from 18 MHz to 68 MHz, with full specification guaranteed at 65 MHz. At this rate, it achieves 455 Mbps per LVDS data channel and 170 MB/s total bandwidth. Operation beyond 68 MHz is not characterized or supported per the datasheet.

Does DS90C363BMTX/NOPB support spread spectrum clocking, and what are the limits?

Yes, DS90C363BMTX/NOPB supports spread spectrum clocking (SSCG) with modulation frequencies up to 100 kHz and deviations of ±2.5% center spread or −5% down spread. This capability is verified across its full 18–68 MHz input clock range and directly affects TxCLK OUT+ and TxCLK OUT− outputs.

How does the R_FB pin configure strobe edge behavior on DS90C363BMTX/NOPB?

On DS90C363BMTX/NOPB, the R_FB pin selects data strobe edge: tying R_FB to VCC configures rising-edge strobe, while connecting it to GND or leaving it unconnected (internal pull-down active) selects falling-edge strobe. This allows seamless interoperability with both DS90CF366 (falling) and rising-edge LVDS receivers.

What power supply domains does DS90C363BMTX/NOPB require, and why are they separated?

DS90C363BMTX/NOPB requires three independent 3.3V supplies: VCC for TTL inputs, PLL VCC for phase-locked loop circuitry, and LVDS VCC for differential output drivers. This separation minimizes noise coupling between digital logic, sensitive PLL, and high-speed analog outputs-critical for jitter performance and EMI control.

Is DS90C363BMTX/NOPB pin-compatible with earlier versions like DS90C363A?

Yes, DS90C363BMTX/NOPB is a pin-for-pin replacement for DS90C363A and backward compatible with DS90C363/DS90CF363. It retains identical 48-pin TSSOP (DGG) footprint, pin mapping, and power domain connections-enabling drop-in upgrades without PCB revision.

DS90C363BMTX/NOPB Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 48-TFSOP (0.240", 6.10mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Applications:: -

Interface:: -

Voltage - Supply:: 3V ~ 3.6V

Supplier Device Package:: 48-TSSOP

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

DS90C363BMTX/NOPB FAQ

1.How can I place an order for DS90C363BMTX/NOPB through Aetrix?

Please submit a Request for Quotation (RFQ) for DS90C363BMTX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for DS90C363BMTX/NOPB reliable?

The price and inventory of DS90C363BMTX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90C363BMTX/NOPB is usually 5 days.

3.What payment methods are accepted for DS90C363BMTX/NOPB?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90C363BMTX/NOPB transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for DS90C363BMTX/NOPB?

DS90C363BMTX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your DS90C363BMTX/NOPB order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for DS90C363BMTX/NOPB?

For technical support, including DS90C363BMTX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90C363BMTX/NOPB requirements.

6.How does Aetrix verify that DS90C363BMTX/NOPB is sourced from the original manufacturer or authorized distributors?

All DS90C363BMTX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90C363BMTX/NOPB meets industry standards.

7.What is the process for return or replacement of DS90C363BMTX/NOPB?

All DS90C363BMTX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90C363BMTX/NOPB, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The DS90C363BMTX/NOPB part is unused and in its original packaging.

Return procedure for DS90C363BMTX/NOPB:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…