Texas Instruments DS90C363MTD

Overview

DS90C363MTD from Texas Instruments is a +3.3V programmable LVDS transmitter for 18-bit flat panel display (FPD) links, converting 21-bit CMOS/TTL input (18 RGB + 3 control) into three LVDS data streams and one LVDS clock stream. It supports 20–65 MHz shift clocks, delivers up to 1.3 Gbps total throughput, and operates from −40°C to +85°C in a low-profile 48-lead TSSOP package.

For engineers reviewing the DS90C363MTD datasheet, DS90C363MTD pinout, DS90C363MTD application, or DS90C363MTD equivalent, this page provides verified technical context, validated pin functions, confirmed FPD Link timing roles, and real-world design implications for XGA-resolution LCD interconnects with EMI-sensitive routing constraints.

Technical Context

The DS90C363MTD implements a PLL-based LVDS transmitter architecture with programmable strobe edge selection (rising or falling) via the R_FB pin. Its internal phase-locked loop generates the LVDS clock output without external components and synchronizes all 21-bit parallel inputs to the TxCLK IN signal.

It converts TTL/CMOS logic-level inputs-including six red, six green, six blue, and three timing signals (FPLINE, FPFRAME, DRDY)-into four differential LVDS outputs: three data pairs (TxOUT+/−) and one clock pair (RTxCLK OUT+/−), each compliant with TIA/EIA-644 standards and exhibiting 290 mV typical differential swing.

Key Specifications

Pinout & Package

DS90C363MTD uses a 48-pin TSSOP package (JEDEC MO-153, TI package code DGG), 12.4–12.6 mm × 6.0–6.2 mm footprint, 1.2 mm max height, with gull-wing leads and exposed thermal pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS FPD Link transmitter applications.

Compared with DS90C383MTD, DS90C363MTD provides optimized XGA support with lower power and cost; versus SN65LVDS31DGKR, it delivers complete FPD Link functionality-including PLL, strobe control, and timing signal handling-without external logic.

Availability

DS90C363MTD is available at Aetrix Electronics and suitable for LCD panel interconnect, industrial HMI display, medical imaging monitor, and automotive infotainment applications requiring stable component supply and long-term lifecycle support.

Supply support for DS90C363MTD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS90C363MTD belongs to TI's Flat Panel Display Link chipset family, designed specifically to replace wide parallel TTL buses in display interfaces with compact, low-EMI LVDS links for industrial, medical, and automotive displays.

FAQ

What is the maximum data rate supported by the DS90C363MTD?

The DS90C363MTD supports a maximum shift clock frequency of 65 MHz, delivering up to 1.3 Gbps total throughput (455 Mbps per LVDS data channel). At this rate, it handles 18-bit RGB plus 3 control bits per clock cycle, enabling single-pixel-per-clock XGA (1024×768) timing with verified timing margins per the SNLS123C datasheet.

Does the DS90C363MTD require external components for its PLL operation?

No, the DS90C363MTD integrates a fully self-contained PLL that requires no external crystals, capacitors, or resistors. The PLL locks to the incoming TxCLK IN signal and generates the synchronized LVDS clock output (RTxCLK OUT+/−), simplifying layout and reducing BOM count compared to discrete clock synthesis solutions.

Can the DS90C363MTD interface directly with 5 V graphics controllers?

No, the DS90C363MTD TTL/CMOS inputs (TxIN[0:20] and FPSHIFT IN) are rated for 3.3 V operation only and are not 5 V tolerant. Interfacing with 5 V controllers requires level-shifting circuitry; however, the device is backward compatible with 5 V FPD Link receivers (e.g., DS90CF564) when used with appropriate voltage translation.

How does the R_FB pin affect DS90C363MTD operation?

The R_FB pin configures the DS90C363MTD's data strobe edge: tying R_FB to V_CC selects rising-edge sampling, while connecting it to GND (or leaving it open, due to internal pull-down) selects falling-edge sampling. This programmability allows direct replacement of both DS90CR563 (rising-edge) and DS90CF563 (falling-edge) transmitters without layout changes.

What is the power consumption of DS90C363MTD in active and power-down modes?

In active mode at 65 MHz worst-case pattern, DS90C363MTD draws 42–55 mA (typical 48 mA). In power-down mode (PWR DWN = low), supply current drops to 10–55 µA (typical 30 µA), reducing total power to <0.5 mW-enabling rapid link disable for display blanking or energy-saving states without affecting upstream logic.