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Texas Instruments DS90C363MTD/NOPB
- Part No.:
- DS90C363MTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90C363MTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,744
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Product details
Overview
DS90C363MTD/NOPB from Texas Instruments is a +3.3V programmable LVDS transmitter for 18-bit flat panel display (FPD) links, converting 21-bit CMOS/TTL input (6R+6G+6B+3 control) into three LVDS data streams and one LVDS clock stream at up to 65 MHz shift clock frequency, supporting XGA (1024×768) single-pixel-per-clock timing in LCD panel interfaces.
For engineers reviewing the DS90C363MTD/NOPB datasheet, DS90C363MTD/NOPB pinout, DS90C363MTD/NOPB application, or DS90C363MTD/NOPB equivalent, this page delivers verified electrical specs, strobe-edge configuration behavior, power-down current (<0.5 mW), TSSOP-48 package mapping, and interoperability details with DS90CF364 receivers - all critical for FPD Link migration from 5V to 3.3V systems.
Technical Context
The DS90C363MTD/NOPB implements a PLL-based LVDS transmitter with programmable data strobe edge (rising or falling) selected via R_FB pin, enabling direct compatibility with legacy 5V FPD Link controllers without layout changes when configured for rising edge. It operates across −40°C to +85°C with single 3.3V supply and integrates dedicated power domains for TTL I/O, LVDS drivers, and PLL circuitry.
Each LVDS data channel delivers up to 455 Mbps at 65 MHz, achieving 170 MB/s aggregate throughput and 1.3 Gbps total link bandwidth while maintaining 290 mV differential output swing compliant with TIA/EIA-644. Channel-to-channel skew is limited to 250 ps, and pulse position jitter is specified within ±0.4 ns for Bit 0 at 65 MHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V nominal; enables direct replacement of 5V FPD Link transmitters using existing 3.3V rails. |
| Data Rate per LVDS Channel | 455 Mbps at 65 MHz clock; supports single-pixel-per-clock XGA (1024×768) RGB+control transmission. |
| Differential Output Swing | 250–450 mV; ensures low EMI and robust noise margin over twisted-pair interconnects. |
| Power-Down Current | <0.5 mW total; reduces system standby power in display sleep modes. |
| Operating Temperature | −40°C to +85°C; qualified for industrial and automotive display module environments. |
| LVDS Compliance | TIA/EIA-644 standard; guarantees interoperability with industry-standard LVDS receivers including DS90CF364. |
| Strobe Edge Programmability | Rising or falling edge via R_FB pin; eliminates need for external level-shifting or logic translation in mixed-edge systems. |
Pinout & Package
DS90C363MTD/NOPB uses a 48-pin TSSOP (DGG) package with 0.5 mm pitch, 12.4–12.6 mm × 6.0–6.2 mm body, and 1.2 mm max height - optimized for high-density PCB layouts in space-constrained display modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TxIN[0:20] | CMOS/TTL Input | 21-bit parallel interface: 6 red, 6 green, 6 blue, plus FPLINE/FPFRAME/DRDY control signals. |
| FPSHIFT IN (TxCLK IN) | Input Clock | Falling-edge strobe by default; rising-edge mode enabled when R_FB = VCC. |
| R_FB | Strobe Select Input | Configures data sampling edge: VCC = rising edge, GND/open = falling edge. |
| TxOUT+[0:2], TxOUT−[0:2] | LVDS Data Outputs | Three differential pairs carrying 18-bit RGB + 3 control bits; each pair rated for 455 Mbps. |
| RTxCLK OUT+, TxCLK OUT− | LVDS Clock Output | Differential transmit clock synchronized to data; enables receiver clock recovery without separate reference. |
| PWR DWN | Power-Down Control | Active-low input that tri-states all LVDS outputs and reduces supply current to <0.5 mW. |
| VCC, LVDS VCC, PLL VCC | Power Supply Inputs | Separate 3.3V domains isolate noise between TTL logic, LVDS drivers, and PLL circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable strobe edge | Eliminates redesign when migrating from DS90CF563 (falling edge) or DS90CR563 (rising edge) transmitters. |
| Single 3.3V supply operation | Removes need for 5V rail in display subsystems, simplifying power architecture and reducing BOM count. |
| Chipset power consumption <250 mW | Enables thermal compliance in sealed LCD enclosures without forced air cooling. |
| Narrow bus reduces cable size | Replaces 21-wire TTL ribbon with 8-wire LVDS (3 data + 1 clock differential pairs), cutting connector cost and EMI. |
| PLL requires no external components | Reduces bill-of-materials and layout area versus discrete clock synthesis solutions. |
Applications
| LCD Panel Interface | XGA Display Module |
|---|---|
Use Scenario: Driving 1024×768 resolution TFT-LCD panels in industrial HMIs where EMI must be minimized and cable routing constrained. IC Role / Device Role / Timing Role: Converts parallel RGB+control signals from graphics controller into serialized LVDS streams with embedded clock for long-reach panel interconnect. Use Value: Enables 1.3 Gbps link bandwidth over 10+ cm twisted-pair cables while meeting CISPR-22 Class B emissions limits. |
Use Scenario: Upgrading legacy 5V FPD Link designs to 3.3V operation in medical imaging displays requiring extended temperature range support. IC Role / Device Role / Timing Role: Drop-in replacement for DS90CF563 with identical pinout and functional timing, configurable via R_FB for backward compatibility. Use Value: Maintains existing PCB layout while reducing power dissipation by ~40% and eliminating 5V supply rail. |
| Automotive Infotainment Display | Embedded Vision System |
Use Scenario: Transmitting video data from SoC to central display unit in vehicle dashboards operating across −40°C to +85°C ambient. IC Role / Device Role / Timing Role: LVDS transmitter providing robust, jitter-tolerant pixel clock and data transport immune to automotive EMI sources. Use Value: Achieves 400 ps skew margin at 65 MHz, accommodating cable length variations and board-level signal integrity challenges. |
Use Scenario: Interfacing FPGA-based image processors to high-resolution LCD viewfinders in portable inspection equipment. IC Role / Device Role / Timing Role: Bridges parallel camera pipeline output to compact LVDS display interface with minimal latency and deterministic timing. Use Value: Delivers sub-nanosecond channel-to-channel skew (250 ps) ensuring pixel-aligned RGB data delivery for accurate color reproduction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS transmitter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90C365MTD/NOPB | Higher maximum clock rate (85 MHz vs. 65 MHz); same 21-bit input, 3-channel LVDS output, TSSOP-48 package. | Supports SXGA (1280×1024) and UXGA (1600×1200) resolutions; requires updated timing constraints in graphics controller firmware. | Select DS90C365MTD/NOPB when migrating beyond XGA resolution or requiring higher pixel clock headroom. |
| SN65LVDS31DR | 4-channel LVDS transmitter (not FPD Link–specific); no integrated strobe programming or FPD control signal mapping; SOIC-16 package. | Requires external logic to handle HSYNC/VSYNC/DRDY timing; suited for generic serial data transport, not display-native protocols. | Choose SN65LVDS31DR only for non-FPD applications where protocol transparency and minimal channel count are priorities. |
Compared with DS90C363MTD/NOPB, DS90C365MTD/NOPB offers higher bandwidth for future-resolution scaling but shares identical pinout and configuration logic, whereas SN65LVDS31DR lacks FPD Link protocol awareness and requires full custom timing implementation.
Availability
DS90C363MTD/NOPB is available at Aetrix Electronics and suitable for industrial HMIs, automotive infotainment displays, and embedded vision systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for DS90C363MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions for display and industrial markets.
The DS90C363MTD/NOPB belongs to TI's Flat Panel Display Link (FPD-Link) product line, engineered specifically to replace wide parallel TTL buses with low-power, low-EMI LVDS serial links in LCD and OLED display interfaces.
FAQ
What is the function of the R_FB pin on the DS90C363MTD/NOPB?
The R_FB pin on the DS90C363MTD/NOPB selects the data strobe edge: when tied to VCC, it configures the device for rising-edge sampling; when grounded or left open (internal pull-down), it enables falling-edge sampling. This programmability allows seamless integration with both legacy rising-edge (e.g., DS90CR563) and falling-edge (e.g., DS90CF563) graphics controllers without hardware modification.
Does the DS90C363MTD/NOPB support 5V-tolerant inputs?
No, the DS90C363MTD/NOPB does not support 5V-tolerant inputs. Its CMOS/TTL inputs operate strictly within 3.3V logic levels (VIH ≥ 2.0 V, VIL ≤ 0.8 V) and must be driven from 3.3V-compatible sources. Direct connection to 5V logic will exceed absolute maximum ratings and risk permanent damage to the DS90C363MTD/NOPB.
Can the DS90C363MTD/NOPB be used without an external crystal or oscillator?
Yes, the DS90C363MTD/NOPB contains an internal PLL that locks to the incoming FPSHIFT IN (TxCLK IN) clock signal and requires no external crystal or oscillator. The PLL is fully integrated and needs no external passive components - the only required input is the 20–65 MHz differential or single-ended TTL clock applied to the FPSHIFT IN pin.
What is the maximum cable length supported by the DS90C363MTD/NOPB at 65 MHz?
The DS90C363MTD/NOPB does not specify a fixed maximum cable length, as performance depends on interconnect quality, termination, and noise environment. However, with proper 100 Ω differential termination and low-skew twisted-pair cable, reliable operation up to 10 meters has been validated in reference designs. Skew margin analysis (RSKM = 400 ps at 65 MHz) accounts for typical cable-induced skew (~10–40 ps/ft) and <250 ps cycle-to-cycle jitter.
How does the DS90C363MTD/NOPB handle power-down mode?
In power-down mode (PWR DWN = low), the DS90C363MTD/NOPB tri-states all LVDS outputs (TxOUT+/− and RTxCLK OUT+/−) and reduces total supply current to less than 0.5 mW. The internal PLL remains active but output drivers are disabled, allowing fast wake-up (<100 ns delay) without re-locking time. This mode is essential for dynamic power management in battery-powered or energy-sensitive display systems.
DS90C363MTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Not For New Designs
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90C363MTD/NOPB FAQ
1.How can I place an order for DS90C363MTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90C363MTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90C363MTD/NOPB reliable?
The price and inventory of DS90C363MTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90C363MTD/NOPB is usually 5 days.
3.What payment methods are accepted for DS90C363MTD/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90C363MTD/NOPB transactions.
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4.How is shipping managed for DS90C363MTD/NOPB?
DS90C363MTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90C363MTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90C363MTD/NOPB?
For technical support, including DS90C363MTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90C363MTD/NOPB requirements.
6.How does Aetrix verify that DS90C363MTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90C363MTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90C363MTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90C363MTD/NOPB?
All DS90C363MTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90C363MTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90C363MTD/NOPB part is unused and in its original packaging.
Return procedure for DS90C363MTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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