My Inquiry
My Account
Texas Instruments DS90C363MTDX
- Part No.:
- DS90C363MTDX
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90C363MTDX.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,039
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90C363MTDX from Texas Instruments is a +3.3V programmable LVDS transmitter for Flat Panel Display (FPD) Link applications, converting 21-bit CMOS/TTL data (18 RGB + 3 control) into three LVDS data streams and one LVDS clock stream. It operates at 20–65 MHz shift clock frequency, delivers up to 1.3 Gbps total throughput, and supports XGA (1024×768) single-pixel-per-clock timing in flat-panel LCD interfaces.
For engineers reviewing the DS90C363MTDX datasheet, DS90C363MTDX pinout, DS90C363MTDX application, or DS90C363MTDX equivalent, this page provides verified functional identity, confirmed TSSOP-48 package mapping, validated 21-input/4-output LVDS interface roles, real-world FPD Link timing constraints, and two technically documented alternative transmitters with strobe-edge and power-supply compatibility notes.
Technical Context
The DS90C363MTDX implements a PLL-based LVDS serializer with programmable data strobe edge selection (rising or falling) via R_FB pin, enabling interoperability with both rising- and falling-edge receivers like DS90CF364. Its transmit clock (TxCLK IN) is embedded as a fourth LVDS differential pair (RTxCLK OUT+/−), synchronized to input data sampling.
It accepts 21 TTL/CMOS inputs - six red, six green, six blue, plus FPLINE, FPFRAME, and DRDY - and maps them across three 7-bit LVDS data channels. The device requires separate supply domains: VCC (TTL I/O), PLL VCC, and LVDS VCC, each with dedicated ground pins to minimize noise coupling between logic and high-speed analog sections.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Single 3.3V rail operation; no level-shifting required for 3.3V graphics controllers. |
| Data Rate | Up to 1.3 Gbps total - Achieved at 65 MHz clock × 21 bits = 1.365 Gbps raw; enables 170 MB/s bandwidth for XGA displays. |
| LVDS Output Swing | 250–450 mV differential - Compliant with TIA/EIA-644 standard; ensures low EMI and robust noise margin over twisted-pair cables. |
| Power Consumption | 42–55 mA typical at 65 MHz - Chipset (TX+RX) draws <250 mW; power-down mode reduces current to <0.5 mW. |
| Operating Temperature | −40°C to +85°C - Qualified for industrial-grade flat-panel display systems including kiosks, medical monitors, and industrial HMIs. |
| Package | TSSOP-48 (DGG) - Low-profile 12.6 mm × 6.1 mm body; JEDEC MO-153 compliant; MSL Level-2-260C-1 YEAR reflow rating. |
| Strobe Edge Control | Programmable via R_FB pin - Pull-high for rising-edge strobe; pull-low or floating (internal pull-down) for falling-edge strobe. |
Pinout & Package
DS90C363MTDX uses a 48-pin Thin Shrink Small Outline Package (TSSOP), designated DGG per JEDEC MO-153, with 0.5 mm pitch, 12.6 mm × 6.1 mm footprint, and maximum 1.2 mm height. Pin 1 is located in Quadrant Q1 per tape-and-reel orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TxIN[0–20] | CMOS/TTL Input | 21-bit parallel data bus: R0–R5, G0–G5, B0–B5, FPLINE, FPFRAME, DRDY - directly interfaces GPU or timing controller outputs. |
| FPSHIFT IN (TxCLK IN) | Input Clock | Falling-edge strobe by default; rising-edge when R_FB = VCC - defines sampling edge for all TxIN bits. |
| R_FB | Strobe Select | Configures strobe edge polarity; internal pull-down allows floating connection for falling-edge mode without PCB change. |
| TxOUT+[0–2], TxOUT−[0–2] | LVDS Data Output | Three differential pairs carrying 7-bit segments of 21-bit input; routed to matched-length twisted pairs on flex cable or board. |
| RTxCLK OUT+, TxCLK OUT− | LVDS Clock Output | Differential transmit clock output; must be routed with same trace length and impedance as data pairs to maintain skew <250 ps. |
| PWR DWN | Power-Down Control | Active-low TTL input; places all LVDS drivers in high-impedance state and reduces supply current to <55 µA. |
| VCC, PLL VCC, LVDS VCC | Supply Inputs | Three independent 3.3V supplies - isolates noise-sensitive PLL and high-speed LVDS driver domains from digital I/O. |
| GND, PLL GND, LVDS GND | Ground Returns | Four TTL GND, two PLL GND, three LVDS GND pins - require separate low-impedance planes to prevent ground bounce coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable strobe edge | Enables drop-in replacement for legacy 5V FPD Link transmitters (e.g., DS90CF563) without redesigning strobe logic or layout. |
| Integrated PLL with no external components | Eliminates need for external crystal or loop filter; reduces BOM count and layout area while maintaining jitter <250 ps at 65 MHz. |
| Narrow 21-bit parallel → 4-channel LVDS conversion | Reduces interconnect width from ~21 traces to 4 differential pairs - cuts flex cable cost, weight, and EMI emissions by >70% vs. TTL buses. |
| Low-power shutdown mode | Draws <0.5 mW total during sleep; critical for battery-powered portable displays and panel power sequencing. |
| ESD protection >7 kV HBM | Protects against handling damage during assembly and field service; avoids need for external TVS diodes on LVDS lines. |
Applications
| Industrial LCD Video Interface | Medical Diagnostic Monitor |
|---|---|
|
Use Scenario: Driving 1024×768 resolution TFT-LCD panels in factory automation HMIs where EMI limits prohibit wide parallel TTL buses. IC Role / Device Role / Timing Role: LVDS serializer converting GPU's 21-bit RGB+control output into noise-immune differential signals over 15 cm flex cable. Use Value: Enables reliable video transmission at 65 MHz with <250 ps channel skew, meeting IEC 61000-4-3 radiated immunity requirements. |
Use Scenario: Transmitting real-time ultrasound image data from FPGA-based beamformer to high-brightness diagnostic display. IC Role / Device Role / Timing Role: High-fidelity pixel clock forwarding and RGB serialization with deterministic 3.0–5.5 ns TxCLK IN→OUT delay for precise frame sync. Use Value: Maintains sub-pixel timing accuracy across temperature (−40°C to +85°C), preventing image tearing or color misalignment. |
| Avionics Cabin Display | Ruggedized Point-of-Sale Terminal |
|
Use Scenario: Interfacing graphics processor to sunlight-readable cockpit display in certified airborne equipment with strict DO-160E emission limits. IC Role / Device Role / Timing Role: EMI-optimized LVDS transmitter using 290 mV swing and controlled slew rate (0.75–1.5 ns transition) to meet Class A conducted emissions. Use Value: Eliminates need for ferrite beads or shielding cans on display cable, reducing SWaP-C and certification test cycles. |
Use Scenario: Connecting ARM-based SoC to 800×480 retail kiosk LCD under frequent thermal cycling and vibration stress. IC Role / Device Role / Timing Role: Robust serializer with >7 kV HBM ESD rating and separate LVDS/PLL/TTL supply domains to withstand electrostatic discharge in public environments. Use Value: Prevents field failures due to operator touch-induced discharge, extending mean time between failures (MTBF) beyond 100,000 hours. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS transmitter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90C383MTDX | 24-bit version (RGB888 + 3 control); identical 20–65 MHz range, same TSSOP-48 package, and pin-compatible pinout except added TxIN[21–23]. | Required for SXGA (1280×1024) or higher resolutions; not suitable for XGA-only designs due to extra input loading and routing overhead. | Select DS90C383MTDX only when migrating to deeper color depth or higher addressability; retains same layout and firmware interface. |
| SN65LVDS31DR | Quad LVDS line driver (no serializer); no internal PLL, no programmable strobe, no 21-bit parallel input - requires external clock domain crossing logic. | Suitable only for point-to-point clock/data forwarding where source already provides serialized LVDS; cannot replace DS90C363MTDX in FPD Link systems. | Choose SN65LVDS31DR only for custom LVDS physical layer extension, not as functional replacement; demands full redesign of timing and data path. |
Compared with DS90C363MTDX, DS90C383MTDX extends resolution support while preserving pinout and power architecture, whereas SN65LVDS31DR lacks serialization capability entirely and serves a fundamentally different system role - making it unsuitable for direct substitution in FPD Link implementations.
Availability
DS90C363MTDX is available at Aetrix Electronics and suitable for industrial HMIs, medical imaging displays, avionics cabin monitors, and ruggedized retail terminals requiring stable component supply across extended product lifecycles.
Supply support for DS90C363MTDX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in display interface solutions.
The DS90C363MTDX belongs to TI's FPD Link chipset family, designed specifically to replace wide, high-noise TTL interfaces in flat-panel display systems with compact, low-EMI LVDS links for industrial and medical applications.
FAQ
What is the function of the R_FB pin on DS90C363MTDX?
The R_FB pin on DS90C363MTDX selects the data strobe edge polarity: tied to VCC for rising-edge sampling, or grounded/floating (internal pull-down) for falling-edge sampling. This programmability allows seamless integration with existing graphics controllers using either strobe convention without modifying timing logic or PCB layout - a key enabler for upgrading from legacy 5V FPD Link transmitters.
Does DS90C363MTDX support XGA resolution at 60 Hz?
Yes, DS90C363MTDX fully supports single-pixel-per-clock XGA (1024×768) timing at 60 Hz, requiring a 65 MHz pixel clock. At this rate, it serializes 21 bits per cycle (18 RGB + 3 control) across three LVDS data lanes and one clock lane, achieving 170 MB/s throughput and meeting the bandwidth and skew requirements defined in the FPD Link specification for stable, flicker-free display operation.
Can DS90C363MTDX operate with a 2.5V supply?
No, DS90C363MTDX requires a nominal 3.3V supply with a specified operating range of 3.0 V to 3.6 V. Its CMOS/TTL input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) and LVDS driver circuitry are optimized for 3.3V logic levels; operation below 3.0 V violates recommended conditions and may cause setup/hold violations, increased jitter, or failure to meet TIA/EIA-644 output swing specifications.
What is the purpose of separate VCC, PLL VCC, and LVDS VCC pins on DS90C363MTDX?
DS90C363MTDX uses three independent 3.3V supply pins to isolate noise-sensitive functional blocks: VCC powers TTL I/O buffers, PLL VCC feeds the phase-locked loop core, and LVDS VCC drives the high-speed differential output stages. This separation prevents switching noise from digital inputs or clock generation from modulating LVDS output common-mode voltage or jitter - a critical design requirement for maintaining signal integrity in high-speed display links.
Is DS90C363MTDX pin-compatible with DS90CF364 receiver?
No, DS90C363MTDX is not pin-compatible with DS90CF364 - they serve complementary roles in the FPD Link chipset (transmitter vs. receiver) and have distinct pin assignments. DS90C363MTDX has 21 TTL inputs and 4 LVDS outputs; DS90CF364 has 4 LVDS inputs and 21 TTL outputs. Their pinouts are mirror-symmetric in function but physically incompatible - requiring separate PCB footprints and routing topologies.
DS90C363MTDX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90C363MTDX FAQ
1.How can I place an order for DS90C363MTDX through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90C363MTDX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90C363MTDX reliable?
The price and inventory of DS90C363MTDX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90C363MTDX is usually 5 days.
3.What payment methods are accepted for DS90C363MTDX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90C363MTDX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90C363MTDX?
DS90C363MTDX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90C363MTDX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90C363MTDX?
For technical support, including DS90C363MTDX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90C363MTDX requirements.
6.How does Aetrix verify that DS90C363MTDX is sourced from the original manufacturer or authorized distributors?
All DS90C363MTDX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90C363MTDX meets industry standards.
7.What is the process for return or replacement of DS90C363MTDX?
All DS90C363MTDX units undergo pre-shipment inspection (PSI). If there is an issue with DS90C363MTDX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90C363MTDX part is unused and in its original packaging.
Return procedure for DS90C363MTDX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90C363MTDX Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
