Texas Instruments DS90C363MTDX/NOPB
- Part No.:
- DS90C363MTDX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90C363MTDX/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,133
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Product details
Overview
DS90C363MTDX/NOPB from Texas Instruments is a +3.3V programmable LVDS transmitter for 18-bit flat panel display (FPD) links, converting 21-bit CMOS/TTL data (18 RGB + 3 control) into three LVDS data streams and one LVDS clock stream at up to 65 MHz shift clock frequency, supporting XGA (1024×768) single-pixel-per-clock timing in LCD display interfaces.
For engineers reviewing the DS90C363MTDX/NOPB datasheet, DS90C363MTDX/NOPB pinout, DS90C363MTDX/NOPB application, or DS90C363MTDX/NOPB equivalent, key selection considerations include programmable rising/falling edge strobe configuration via R_FB pin, 290 mV LVDS differential output swing, TSSOP-48 package compatibility with FPD Link receiver DS90CF364, and operation across −40°C to +85°C industrial temperature range.
Technical Context
The DS90C363MTDX/NOPB implements a PLL-based LVDS transmitter architecture that embeds a transmit clock alongside three 7-bit LVDS data lanes (21 total bits), with precise pulse positioning (e.g., TPPos0 = −0.4 to 0.3 ns at 65 MHz) and channel-to-channel skew ≤250 ps. It accepts TTL/CMOS inputs at 3.0–3.6 V and drives 100 Ω differential loads.
Strobe edge selection is hardware-configured via R_FB pin (VCC = rising edge, GND/open = falling edge), enabling interoperability with both rising- and falling-edge receivers without translation logic. Power-down mode reduces total current to <0.5 mW while tri-stating LVDS outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Single 3.3 V rail powers TTL inputs, PLL, and LVDS drivers; no level-shifting required. |
| Data Rate | Up to 1.3 Gbps aggregate - 455 Mbps per LVDS lane × 3 lanes + clock, enabling 170 MB/s throughput at 65 MHz. |
| Differential Output Swing | 250–450 mV - Compliant with TIA/EIA-644 LVDS standard; ensures low EMI and noise immunity over cable interconnects. |
| Operating Temperature | −40°C to +85°C - Qualified for industrial-grade flat panel display systems including embedded HMI and medical displays. |
| Power Consumption | 42–55 mA typical at 65 MHz - Chipset (with DS90CF364) draws <250 mW total, reducing thermal load in space-constrained modules. |
| Strobe Edge Control | Hardware-selectable via R_FB pin - Enables direct interface with diverse graphics controllers without FPGA glue logic. |
| ESD Rating | >7 kV HBM - Robust handling during assembly and field service in production environments. |
Pinout & Package
DS90C363MTDX/NOPB is housed in a 48-pin TSSOP (DGG) package, 12.6 mm × 6.1 mm × 1.2 mm max height, RoHS-compliant with Sn lead finish and MSL Level-2 moisture sensitivity rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TxIN[0:20] | CMOS/TTL Input | 21-bit parallel input: 6R/6G/6B + FPLINE/FPFRAME/DRDY (HSYNC/VSYNC/ENA); not 5V-tolerant. |
| FPSHIFT IN (TxCLK IN) | Input Clock | Falling-edge strobe clock input (default); rising-edge mode enabled by R_FB = VCC. |
| R_FB | Strobe Select | Configures strobe edge polarity: VCC → rising edge; GND/open → falling edge (no external pull-up/down needed). |
| TxOUT+[0:2], TxOUT−[0:2] | LVDS Data Output | Three differential LVDS data pairs carrying 7-bit segments of 21-bit input; 100 Ω termination required. |
| RTxCLK OUT+, TxCLK OUT− | LVDS Clock Output | Differential transmit clock output synchronized to data; enables clock-forwarding architecture for jitter-tolerant recovery. |
| PWR DWN | Power-Down Control | Active-low TTL input; places all LVDS outputs in high-impedance state and reduces supply current to <0.5 mW. |
| VCC, PLL VCC, LVDS VCC | Power Supply | Separate 3.3 V rails for TTL I/O (3 pins), PLL core (1 pin), and LVDS drivers (1 pin) minimize noise coupling. |
| GND, PLL GND, LVDS GND | Ground | Dedicated ground returns (4 TTL GND, 2 PLL GND, 3 LVDS GND) ensure clean reference for mixed-signal operation. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable strobe edge | Hardware-selectable rising/falling edge via R_FB pin eliminates need for external strobe inversion logic. |
| Integrated PLL with no external components | Eliminates external loop filter or crystal; simplifies layout and reduces BOM count in display timing circuits. |
| Narrow bus architecture | Replaces 21-wire TTL interface with 8-wire LVDS (3 data pairs + 1 clock pair), cutting cable size, weight, and cost. |
| Low EMI LVDS signaling | 290 mV differential swing and tight skew control (<250 ps) suppress radiated emissions in EMI-sensitive display enclosures. |
| Industrial temperature operation | Validated from −40°C to +85°C, supporting reliable performance in automotive infotainment, industrial HMIs, and medical monitors. |
Applications
| Embedded LCD Display Interface | XGA Resolution Timing Bridge |
|---|---|
|
Use Scenario: Driving 1024×768 TFT-LCD panels in industrial HMIs where space and EMI are constrained. IC Role / Device Role / Timing Role: LVDS transmitter converting parallel RGB+control signals from MCU/FPGA to serialized differential format for panel cable transmission. Use Value: Enables single-pixel-per-clock XGA timing with <250 ps channel skew, ensuring pixel integrity over 30 cm flex cables. |
Use Scenario: Upgrading legacy 5V FPD Link designs to 3.3V operation while retaining existing PCB layout where possible. IC Role / Device Role / Timing Role: Drop-in compatible transmitter replacing DS90CF563; R_FB pin allows backward compatibility with rising-edge controllers. Use Value: Eliminates need for level shifters or redesign-only VCC change and optional R_FB tie-down required for falling-edge systems. |
| VGA/SVGA Display Expansion | Medical Imaging Display Link |
|
Use Scenario: Extending VGA (640×480) or SVGA (800×600) video from embedded GPU to remote display module. IC Role / Device Role / Timing Role: High-speed serializer providing robust clock-forwarding link with built-in PLL lock detection and power-down control. Use Value: Supports >20 MHz pixel clocks with <10 ns setup/hold margin at receiver, enabling stable image rendering under thermal stress. |
Use Scenario: Transmitting diagnostic imaging data (e.g., ultrasound, endoscopy) to high-brightness clinical displays requiring EMI resilience. IC Role / Device Role / Timing Role: Low-jitter LVDS transmitter meeting IEC 60601-1 EMC requirements via controlled slew rate (0.75–1.5 ns) and differential signaling. Use Value: >7 kV HBM ESD rating and −40°C to +85°C operation ensure reliability in sterilized, temperature-cycled clinical environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS transmitter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90C383MTDX/NOPB | 24-bit FPD Link transmitter (vs. 21-bit); supports UXGA (1600×1200) at 85 MHz; higher power (65 mA typ @ 85 MHz). | Required for higher-resolution panels beyond XGA; not pin-compatible due to additional data pins and different pinout. | Select DS90C383MTDX/NOPB only when expanding to UXGA or SXGA resolution with matching receiver (DS90CF384). |
| SN65LVDS31DR | Quad LVDS line driver (4 channels), no integrated PLL or clock forwarding; requires external clock source and timing management. | Suitable for custom serial protocols or non-FPD applications; lacks FPLINE/FPFRAME/DRDY mapping and strobe programming. | Choose SN65LVDS31DR for generic LVDS point-to-point links where FPD Link protocol compliance is unnecessary. |
Compared with DS90C363MTDX/NOPB, DS90C383MTDX/NOPB delivers higher bandwidth for larger displays but demands PCB redesign, while SN65LVDS31DR offers flexibility in non-standard protocols but shifts timing responsibility to system-level design.
Availability
DS90C363MTDX/NOPB is available at Aetrix Electronics and suitable for embedded LCD display interfaces, industrial HMI timing bridges, and medical imaging display links requiring stable component supply and long-term lifecycle support.
Supply support for DS90C363MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in display interface solutions.
The DS90C363MTDX/NOPB belongs to TI's Flat Panel Display (FPD) Link chipset family, designed specifically to replace wide parallel TTL buses with compact, low-EMI LVDS links for LCD and OLED display modules.
FAQ
What is the primary function of the DS90C363MTDX/NOPB in an FPD Link system?
The DS90C363MTDX/NOPB serves as a +3.3V LVDS transmitter that converts 21-bit parallel CMOS/TTL data (18 RGB + 3 control signals) into three LVDS data streams and one LVDS clock stream. It enables high-speed, low-EMI transmission over flexible cables to LCD panels, forming the transmit half of the FPD Link chipset paired with DS90CF364. Its core role is timing-critical serialization for XGA-resolution displays.
How does the R_FB pin configure strobe edge behavior on the DS90C363MTDX/NOPB?
The R_FB pin on the DS90C363MTDX/NOPB determines whether the device uses rising-edge or falling-edge data strobing. When R_FB is tied to VCC, the DS90C363MTDX/NOPB operates in rising-edge strobe mode; when connected to GND or left unconnected (internal pull-down activates), it defaults to falling-edge strobe mode. This hardware-selectable feature ensures compatibility with diverse graphics controllers without firmware or logic changes.
Can the DS90C363MTDX/NOPB be used as a direct replacement for the 5V DS90CF563 transmitter?
The DS90C363MTDX/NOPB is backward compatible with DS90CF563 in functional capability but requires voltage and pin-connection adjustments. It operates at 3.3 V (not 5 V), and its R_FB pin replaces a former VCC connection on DS90CF563. For rising-edge systems, no layout change is needed; for falling-edge systems, R_FB must be grounded. The DS90C363MTDX/NOPB is not 5V-tolerant on inputs.
What package type and mounting details apply to the DS90C363MTDX/NOPB?
The DS90C363MTDX/NOPB uses a 48-pin TSSOP package (JEDEC MO-153, TI package code DGG), measuring 12.6 mm × 6.1 mm × 1.2 mm max height. It ships in large tape-and-reel format (1000 units/reel), with Q1 pin-1 orientation, Sn lead finish, and MSL Level-2 rating (260°C peak reflow). Land pattern and stencil design guidelines are provided in TI's DGG0048A mechanical drawing.
Does the DS90C363MTDX/NOPB support power-down mode, and how is it activated?
Yes, the DS90C363MTDX/NOPB supports hardware-controlled power-down mode. Asserting the PWR DWN pin low places all LVDS outputs in high-impedance state and reduces total supply current to <0.5 mW. This feature enables dynamic power gating in battery-powered or thermally sensitive display systems, with a 100 ns power-down delay specified in the datasheet.
DS90C363MTDX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90C363MTDX/NOPB FAQ
1.How can I place an order for DS90C363MTDX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90C363MTDX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90C363MTDX/NOPB reliable?
The price and inventory of DS90C363MTDX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90C363MTDX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90C363MTDX/NOPB?
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4.How is shipping managed for DS90C363MTDX/NOPB?
DS90C363MTDX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90C363MTDX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90C363MTDX/NOPB?
For technical support, including DS90C363MTDX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90C363MTDX/NOPB requirements.
6.How does Aetrix verify that DS90C363MTDX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90C363MTDX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90C363MTDX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90C363MTDX/NOPB?
All DS90C363MTDX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90C363MTDX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90C363MTDX/NOPB part is unused and in its original packaging.
Return procedure for DS90C363MTDX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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