My Inquiry
My Account
Texas Instruments DS90CF364AMTD/NOPB
- Part No.:
- DS90CF364AMTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CF364AMTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,664
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90CF364AMTD/NOPB from Texas Instruments is a +3.3V LVDS receiver for 18-bit Flat Panel Display (FPD) Link applications, converting three LVDS data streams into 21-bit parallel CMOS/TTL output (6R/6G/6B + HSYNC/VSYNC/DE) with 65 MHz clock support and falling-edge strobe timing. It operates across −10°C to +70°C, consumes <142 mW at 65 MHz grayscale, and integrates a no-external-component PLL.
For engineers reviewing the DS90CF364AMTD/NOPB datasheet, DS90CF364AMTD/NOPB pinout, DS90CF364AMTD/NOPB application, or DS90CF364AMTD/NOPB equivalent, this device serves as a key interface IC in LCD timing control subsystems requiring EMI-resistant high-speed serial-to-parallel conversion, precise setup/hold timing on TTL outputs, and low-power operation in compact TSSOP-48 packaging.
Technical Context
The DS90CF364AMTD/NOPB implements a dedicated LVDS-to-TTL conversion pipeline optimized for FPD-Link timing integrity: its internal PLL locks to the incoming LVDS clock (RxCLK IN±), regenerates a clean TTL RxCLK OUT with 50% duty cycle, and aligns 21 parallel outputs using a falling-edge strobe synchronized to that clock. Input skew margin is 500 ps at 65 MHz, accommodating interconnect skew and jitter ≤250 ps.
It supports worst-case toggling at 65 MHz (1.3 Gbps throughput, 170 MB/s bandwidth) while maintaining best-in-class set/hold times on RxOUT signals and enabling power-down mode (<200 µW). The receiver accepts LVDS differential inputs compliant with TIA/EIA-644 and drives CMOS/TTL loads with VOH ≥2.7 V and VOL ≤0.3 V under specified conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Ensures stable operation with standard +3.3V rail; tolerates up to 100 mVPP supply noise. |
| Data Width & Format | 18-bit RGB + 3 control (HSYNC/VSYNC/DE) - Maps directly to common LCD panel timing requirements without translation logic. |
| Max Data Rate | 65 MHz clock, 1.3 Gbps aggregate - Supports SXGA resolution at 60 Hz with dual-pixel capability. |
| Power Consumption | 78–90 mA typical at 65 MHz - Enables thermal management in space-constrained display modules. |
| Input Skew Margin | 500 ps at 65 MHz - Allows up to ~12.5 inches of differential pair length mismatch in FR-4 PCB routing. |
| ESD Rating | >7 kV HBM - Provides robust handling during assembly and field operation in industrial display environments. |
| Operating Temperature | −10°C to +70°C - Validated for commercial-grade flat-panel display controller boards and embedded HMI systems. |
Pinout & Package
DS90CF364AMTD/NOPB uses a 48-pin TSSOP (DGG) package, 12.4 mm × 6.1 mm × 1.2 mm max height, JEDEC MO-153 compliant, with exposed pad not present and moisture sensitivity level 2 (260°C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN+ / RxIN− (×3) | LVDS differential data inputs | Accept three serialized LVDS data lanes (e.g., from DS90C363A transmitter); require 100 Ω termination. |
| RxCLK IN+ / RxCLK IN− | LVDS differential clock input | Synchronizes internal PLL; determines maximum pixel clock rate and data valid window alignment. |
| RxCLK OUT | TTL-level clock output | Falling edge acts as data strobe for all 21 parallel outputs; 50% duty cycle ensures balanced timing margins. |
| RxOUT[0:20] | CMOS/TTL parallel outputs | 21-bit bus: bits 0–5 = R0–R5, 6–11 = G0–G5, 12–17 = B0–B5, 18–20 = HSYNC/VSYNC/DE (FPLINE/FPFRAME/DRDY). |
| PWR DOWN | Active-low power-down control | Drives all RxOUT low when asserted; reduces current to <55 µA - enables dynamic power gating in display sleep modes. |
| VCC / GND (×4 / ×5) | CMOS/TTL I/O supply & ground | Dedicated power/ground pins minimize switching noise coupling into sensitive LVDS and PLL sections. |
| PLL VCC / PLL GND (×1 / ×2) | PLL core supply & ground | Isolated analog supply domain improves jitter performance and lock stability of internal clock recovery circuitry. |
| LVDS VCC / LVDS GND (×1 / ×3) | LVDS input receiver supply & ground | Separate biasing ensures consistent common-mode range and input threshold accuracy across temperature. |
Key Features
| Feature | Design Value |
|---|---|
| Falling-edge strobe output | Eliminates need for external clock inversion logic when interfacing with rising-edge-latched display controllers. |
| No-external-component PLL | Reduces BOM count and layout area; eliminates tuning capacitors or resistors required by discrete PLL solutions. |
| Best-in-class RxOUT set/hold times | Enables reliable sampling at 65 MHz without additional timing buffers or delay compensation circuits. |
| Low power-down current (<200 µW) | Supports ultra-low-power display suspend states in battery-powered portable devices and kiosks. |
| Integrated ESD protection (>7 kV HBM) | Meets IEC 61000-4-2 Level 4 system-level ESD immunity without external TVS diodes on LVDS lines. |
Applications
| Industrial LCD Controller Board | Medical Diagnostic Display Interface |
|---|---|
Use Scenario: Driving 1024×768 (XGA) or 1280×1024 (SXGA) TFT panels in factory automation HMIs with long cable runs between controller and panel. IC Role / Device Role / Timing Role: LVDS-to-TTL serializer receiver; provides pixel clock regeneration, data deskewing, and parallel output timing alignment. Use Value: Replaces wide, noisy TTL buses with compact 3+1 LVDS pairs, reducing EMI emissions by >20 dB and enabling longer interconnects (>3 m) without signal integrity loss. |
Use Scenario: Integrating high-resolution grayscale imaging displays in ultrasound or MRI console systems requiring deterministic frame timing and low jitter. IC Role / Device Role / Timing Role: Timing-critical FPD-Link receiver ensuring sub-nanosecond data valid windows for real-time image rendering pipelines. Use Value: Delivers 500 ps input skew margin and <250 ps cycle-to-cycle jitter tolerance - guarantees pixel-perfect synchronization across multi-panel diagnostic displays. |
| Automotive Infotainment Head Unit | Avionics Cabin Display Module |
Use Scenario: Connecting SoC-based graphics processors to 7-inch or 10.1-inch automotive dash displays operating in extended temperature environments. IC Role / Device Role / Timing Role: Robust LVDS receiver supporting −10°C to +70°C operation with integrated power-down for display blanking during ignition cycles. Use Value: Enables seamless display wake-up within 10 ms (RPDD = 1 µs) and maintains <142 mW active power - critical for thermal budget in sealed head unit enclosures. |
Use Scenario: Interfacing flight management system video outputs to ruggedized cabin monitors in commercial aircraft with strict DO-160 lightning-induced transient immunity. IC Role / Device Role / Timing Role: ESD-hardened FPD-Link receiver providing fault-tolerant serial link termination and latch-up immune CMOS/TTL outputs. Use Value: >7 kV HBM ESD rating and separate LVDS/PLL/TTL supply domains prevent single-point failures during in-flight electrical disturbances. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS-to-TTL FPD-Link receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF364MTD/NOPB | Same silicon die, identical electrical specs; differs only in tape-and-reel packaging (1000 pcs vs. tube). | No functional difference; selected when automated SMT placement requires reel format. | Choose DS90CF364MTD/NOPB for high-volume production lines using pick-and-place feeders. |
| SN75LVDS83B | 18-bit FPD-Link receiver with 85 MHz max clock, higher power (160 mW), no integrated PLL - requires external clock buffer. | Supports higher resolutions (UXGA) but increases board area and component count due to external PLL requirement. | Choose SN75LVDS83B only if >65 MHz pixel clock or tighter jitter specs (<150 ps) are mandatory. |
Compared with DS90CF364AMTD/NOPB, DS90CF364MTD/NOPB offers identical performance in reel format for volume manufacturing, while SN75LVDS83B trades higher speed and jitter performance for increased complexity and power - making DS90CF364AMTD/NOPB optimal for cost-sensitive, thermally constrained XGA/SXGA display interfaces.
Availability
DS90CF364AMTD/NOPB is available at Aetrix Electronics and suitable for industrial LCD controller boards, medical diagnostic displays, automotive infotainment head units, avionics cabin displays, and embedded HMI systems requiring stable component supply and long-term lifecycle continuity.
Supply support for DS90CF364AMTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in high-reliability interface and signal chain solutions.
The DS90CF364AMTD/NOPB belongs to TI's FPD-Link family, designed specifically to replace bulky parallel TTL interfaces in flat-panel display systems with robust, low-EMI LVDS serial links - targeting display manufacturers seeking reduced cable count, lower radiated emissions, and simplified PCB routing.
FAQ
What is the primary function of the DS90CF364AMTD/NOPB in an FPD-Link system?
The DS90CF364AMTD/NOPB functions as an LVDS-to-TTL parallel receiver, converting three serialized LVDS data streams and one LVDS clock into 21-bit CMOS/TTL parallel output (18-bit RGB + 3 control signals) with a falling-edge strobe. It recovers timing via an integrated PLL and is optimized for driving LCD timing controllers in XGA/SXGA displays. Its design eliminates the need for external clock buffers or translation logic when paired with compatible transmitters like DS90C363A.
Does the DS90CF364AMTD/NOPB require external components for PLL operation?
No, the DS90CF364AMTD/NOPB features a fully integrated PLL that requires no external capacitors, resistors, or crystals. The PLL locks directly to the incoming LVDS clock (RxCLK IN±) and generates a clean TTL RxCLK OUT with 50% duty cycle. This integration reduces bill-of-materials cost, simplifies layout, and improves reliability compared to discrete PLL implementations - a key differentiator confirmed in TI's SNLS040I datasheet Section 1 "Features".
What is the maximum supported pixel clock frequency for DS90CF364AMTD/NOPB?
The DS90CF364AMTD/NOPB supports a maximum shift clock frequency of 65 MHz, as specified in the "Features" section and verified in Receiver Switching Characteristics tables (e.g., RCOH, RCOL, RCCD parameters tested at f = 65 MHz). At this rate, it delivers 1.3 Gbps aggregate throughput (170 MB/s bandwidth), sufficient for SXGA (1280×1024) at 60 Hz with dual-pixel mode. Operation beyond 65 MHz is not characterized or guaranteed.
How does the power-down mode affect output behavior in DS90CF364AMTD/NOPB?
When the PWR DOWN pin is driven low, the DS90CF364AMTD/NOPB enters power-down mode, reducing supply current to ≤55 µA and forcing all 21 RxOUT signals low - including RGB data and HSYNC/VSYNC/DE control lines. This behavior is explicitly documented in Electrical Characteristics (ICCRZ) and Figure 12 (Power Down Delay). Outputs remain latched low until PWR DOWN is deasserted, enabling safe display blanking without external bus-hold circuitry.
Is DS90CF364AMTD/NOPB compatible with standard TIA/EIA-644 LVDS signaling?
Yes, the DS90CF364AMTD/NOPB is fully compliant with the TIA/EIA-644 LVDS standard, as stated in the "Features" list and confirmed in Absolute Maximum Ratings and LVDS RECEIVER DC SPECIFICATIONS sections. Its differential input thresholds (VTH = ±100 mV), common-mode range (0–2.4 V), and input current limits (±10 µA) meet TIA/EIA-644 requirements, ensuring interoperability with any standard LVDS transmitter - including TI's DS90C363A and third-party equivalents.
DS90CF364AMTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF364AMTD/NOPB FAQ
1.How can I place an order for DS90CF364AMTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF364AMTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF364AMTD/NOPB reliable?
The price and inventory of DS90CF364AMTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF364AMTD/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CF364AMTD/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF364AMTD/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CF364AMTD/NOPB?
DS90CF364AMTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF364AMTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF364AMTD/NOPB?
For technical support, including DS90CF364AMTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF364AMTD/NOPB requirements.
6.How does Aetrix verify that DS90CF364AMTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF364AMTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF364AMTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF364AMTD/NOPB?
All DS90CF364AMTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF364AMTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF364AMTD/NOPB part is unused and in its original packaging.
Return procedure for DS90CF364AMTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90CF364AMTD/NOPB Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
