Texas Instruments DS90CF364AMTDX

Overview

DS90CF364AMTDX from Texas Instruments is a +3.3V LVDS receiver IC for 18-bit Flat Panel Display (FPD) Link applications, converting three LVDS data streams into 21-bit CMOS/TTL parallel output (6R/6G/6B + HSYNC/VSYNC/DE) with 65 MHz clock support and falling-edge strobe timing. It operates across −10°C to +70°C, consumes <142 mW at 65 MHz grayscale, and integrates a component-free PLL.

For engineers reviewing the DS90CF364AMTDX datasheet, DS90CF364AMTDX pinout, DS90CF364AMTDX application, or DS90CF364AMTDX equivalent, key selection considerations include its 48-pin TSSOP package, 21-bit FPD-Link receiver role, power-down mode (<200 µW), LVDS input compliance (TIA/EIA-644), and compatibility with DS90C363A transmitters in LCD timing interfaces.

Technical Context

The DS90CF364AMTDX implements a dedicated LVDS-to-TTL conversion pipeline optimized for flat-panel display interconnects, featuring a built-in PLL that locks to incoming LVDS clock without external components and generates a synchronized TTL clock output with falling-edge strobe behavior. Its internal data sampling window delivers best-in-class set/hold times on RxOUT signals, enabling robust timing margin at 65 MHz.

It supports 20–65 MHz shift clock range with 50% duty cycle on RxCLK OUT, handles up to 1.3 Gbps LVDS data throughput (170 MB/s), and maintains ESD robustness (>7 kV HBM). The receiver accepts differential LVDS inputs referenced to LVDS VCC/GND and drives CMOS/TTL outputs powered by separate VCC/GND rails, ensuring noise isolation between analog and digital domains.

Key Specifications

Pinout & Package

DS90CF364AMTDX uses a 48-pin TSSOP (DGG) package, 12.4 mm × 6.1 mm × 1.2 mm max height, RoHS-compliant with Sn lead finish and MSL Level-2 rating (260°C peak reflow).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPD-Link receiver applications.

Compared with DS90CF384AMTDX and SN65LVDS32, DS90CF364AMTDX uniquely delivers production-ready 18-bit FPD-Link reception in a compact 48-pin package with integrated PLL and falling-edge strobe-reducing system-level design effort versus generic receivers and avoiding over-specification versus 24-bit alternatives.

Availability

DS90CF364AMTDX is available at Aetrix Electronics and suitable for industrial LCD timing interfaces, automotive infotainment displays, medical diagnostic monitors, and embedded vision systems requiring stable component supply and long-term lifecycle support.

Supply support for DS90CF364AMTDX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in display interface solutions and high-speed serial link design.

The DS90CF364AMTDX belongs to TI's FPD-Link family, engineered specifically to replace bulky parallel TTL interfaces in flat-panel displays by delivering robust, low-EMI, high-bandwidth LVDS serialization/deserialization with minimal external components.

FAQ

What is the primary function of the DS90CF364AMTDX in a display system?

The DS90CF364AMTDX functions as an 18-bit FPD-Link LVDS receiver that converts three serialized LVDS data streams and one LVDS clock into 21-bit parallel CMOS/TTL output (6R/6G/6B + HSYNC/VSYNC/DE), with a falling-edge strobe clock for synchronous latching. It enables high-speed, low-noise video transmission between graphics processors and flat-panel displays while reducing cable count and EMI.

Does the DS90CF364AMTDX require external components for PLL operation?

No, the DS90CF364AMTDX integrates a fully self-contained PLL that locks to the incoming LVDS clock without any external capacitors, resistors, or crystal components. This simplifies layout, reduces BOM cost, and improves reliability compared to discrete PLL implementations - a key feature confirmed in the SNLS040I datasheet Section 1 "Features".

What is the maximum supported data rate and resolution for DS90CF364AMTDX?

The DS90CF364AMTDX supports up to 1.3 Gbps total data throughput (170 MB/s) at 65 MHz clock rate, sufficient for XGA (1024×768) and dual-pixel SXGA (1280×1024) resolutions with 18-bit color depth. Its 21-bit output bus maps directly to industry-standard FPD-Link timing, as verified in Figure 11 and Table 1 of the SNLS040I datasheet.

How does the power-down mode operate on the DS90CF364AMTDX?

The DS90CF364AMTDX enters ultra-low-power mode when the PWR DOWN pin is driven low, reducing supply current to <200 µW (max) while forcing all RxOUT pins to logic low. Outputs remain in this state until PWR DOWN is returned high, after which the PLL relocks within 10 ms - behavior specified in Electrical Characteristics Table and Figure 12 of SNLS040I.

Is the DS90CF364AMTDX pin-compatible with other devices in the DS90CFxxA family?

No, the DS90CF364AMTDX is not pin-compatible with DS90CF384AMTDX or earlier DS90CF364 variants. It uses a 48-pin TSSOP (DGG) package, whereas DS90CF384A uses 56-pin TSSOP. Pin counts, signal assignments, and power rail allocations differ - confirmed by comparing Figures 16–17 and Pin Descriptions sections in SNLS040I.