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Texas Instruments DS90CF364AMTDX/NOPB
- Part No.:
- DS90CF364AMTDX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CF364AMTDX/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,545
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Product details
Overview
DS90CF364AMTDX/NOPB from Texas Instruments is a +3.3V LVDS receiver for 18-bit Flat Panel Display (FPD) Link applications, converting three LVDS data streams (up to 1.3 Gbps / 170 MB/s) into parallel 21-bit CMOS/TTL output (6R+6G+6B+HSYNC/VSYNC/DE). It operates at 20–65 MHz clock rates, features falling-edge strobe output, and targets LCD timing controller interfaces in industrial and embedded display systems.
For engineers reviewing the DS90CF364AMTDX/NOPB datasheet, DS90CF364AMTDX/NOPB pinout, DS90CF364AMTDX/NOPB application, or DS90CF364AMTDX/NOPB equivalent, this page delivers verified technical context, package-validated pin functions, real-world timing margins, power-down behavior, and direct alternatives for FPD Link receiver selection in VGA–SXGA display designs.
Technical Context
The DS90CF364AMTDX/NOPB implements a PLL-based LVDS-to-TTL conversion architecture with no external components required. Its internal phase-locked loop locks to the incoming LVDS clock (RxCLK IN±), generating a synchronized TTL clock output (RxCLK OUT) with falling-edge strobe timing for reliable sampling of 21-bit parallel data.
It supports worst-case data valid windows up to 750 ps at 25 MHz and 500 ps at 65 MHz, accommodating interconnect skew, ISI, and sub-250 ps cycle-to-cycle jitter. The receiver maintains best-in-class set/hold times on RxOUT signals and delivers <142 mW typical power consumption at 65 MHz grayscale operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface Type | LVDS receiver with TTL/CMOS parallel output - converts 3 LVDS pairs into 21-bit FPD Link data path. |
| Data Width | 21-bit parallel output: 6 red, 6 green, 6 blue, plus HSYNC, VSYNC, and DE control signals. |
| Max Data Rate | 1.3 Gbps aggregate throughput - enables SXGA resolution at 60 Hz with dual-pixel support. |
| Operating Clock Range | 20–65 MHz shift clock - compatible with VGA (25 MHz), SVGA (36 MHz), XGA (65 MHz), and dual-pixel SXGA. |
| Supply Voltage | +3.0 V to +3.6 V (nominal 3.3 V) - requires separate LVDS VCC, PLL VCC, and TTL VCC rails. |
| Power Consumption | 78–90 mA worst-case supply current at 65 MHz; <200 µW max in power-down mode. |
| ESD Rating | >7 kV HBM, >700 V EIAJ - suitable for handling in standard assembly environments without special precautions. |
Pinout & Package
DS90CF364AMTDX/NOPB uses a 48-pin TSSOP (DGG) package, 12.4 mm × 6.1 mm × 1.2 mm max height, JEDEC MO-153 compliant, with exposed pad not present. Pin 1 located in Q1 quadrant per tape-and-reel specification.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN+, RxIN− (×3) | LVDS differential data inputs | Three pairs accepting serialized FPD Link data; common-mode range 0–2.4 V, differential threshold ±100 mV. |
| RxCLK IN+, RxCLK IN− | LVDS differential clock input | Accepts embedded clock from DS90C363A or compatible transmitter; drives internal PLL. |
| RxCLK OUT | TTL-level clock output | Falling-edge strobe synchronized to recovered clock; 5.0–9.0 ns high/low time at 65 MHz. |
| RxOUT[0:20] | TTL/CMOS parallel data outputs | 21-bit bus: bits 0–5 = R, 6–11 = G, 12–17 = B, 18 = HSYNC, 19 = VSYNC, 20 = DE (Data Enable). |
| PWR DOWN | Active-low power-down control | Drives all RxOUT low when asserted; <55 µA quiescent current; 1 µs delay to enter power-down state. |
| VCC (×4), GND (×5) | TTL I/O supply and ground | Dedicated power/ground pins minimize switching noise on parallel outputs; decoupling required per pin group. |
| LVDS VCC, LVDS GND (×3) | LVDS input supply and ground | Isolated analog rail for LVDS receivers; improves noise immunity on high-speed differential inputs. |
| PLL VCC, PLL GND (×2) | PLL core supply and ground | Separate low-noise supply domain for phase-locked loop; critical for jitter performance and lock stability. |
Key Features
| Feature | Design Value |
|---|---|
| No external PLL components | Integrated loop filter and VCO eliminate discrete capacitors/resistors - reduces BOM count and layout sensitivity. |
| Falling-edge strobe output | RxCLK OUT falling edge directly clocks downstream latch or FPGA register - eliminates need for external inversion logic. |
| Best-in-class RxOUT set/hold times | 7.3 ns setup / 6.3 ns hold relative to RxCLK OUT edge - enables robust timing closure with standard CMOS loads. |
| Low-power grayscale operation | 43–60 mA supply current at 65 MHz with 16-grayscale pattern - optimized for real-world LCD video traffic, not worst-case toggling. |
| Interoperability with rising/falling-edge transmitters | Direct compatibility with DS90C363A (falling-edge) and DS90C383A (rising-edge) without translation logic - simplifies system-level design reuse. |
Applications
| Industrial LCD Timing Controller Interface | VGA/SVGA Embedded Display Module |
|---|---|
Use Scenario: Driving 1024×768 (XGA) or 800×600 (SVGA) TFT panels in factory HMIs, medical displays, and test equipment using legacy TTL interface ASICs. IC Role / Device Role / Timing Role: Converts serialized LVDS from graphics processor or SoC to parallel RGB+control signals synchronized to falling-edge strobe. Use Value: Reduces EMI and cable bulk vs. wide parallel TTL buses while maintaining timing margin for 65 MHz pixel clocks. |
Use Scenario: Replacing aging discrete TTL drivers in cost-sensitive VGA monitor designs requiring backward compatibility with analog sync signals. IC Role / Device Role / Timing Role: Receives LVDS stream from DS90C363A transmitter and regenerates TTL-level HSYNC/VSYNC/DE with precise setup/hold alignment. Use Value: Enables drop-in upgrade path from 24-bit to 18-bit FPD Link without redesigning timing controller logic or PCB layout. |
| Dual-Pixel SXGA Display Subsystem | Automotive Instrument Cluster Backlight Interface |
Use Scenario: Supporting dual-pixel-per-clock SXGA (1280×1024) displays in avionics or industrial control panels where bandwidth exceeds single-pixel LVDS limits. IC Role / Device Role / Timing Role: Recovers 65 MHz clock and 21-bit data from two-lane LVDS source, delivering pixel-aligned RGB outputs with <1.4 ns strobe position variation. Use Value: Achieves 170 MB/s effective bandwidth - sufficient for dual-pixel SXGA at 60 Hz with blanking overhead. |
Use Scenario: Interfacing automotive-grade graphics SoCs to segmented LED backlight drivers requiring precise DE (Data Enable) timing for PWM dimming synchronization. IC Role / Device Role / Timing Role: Provides deterministic DE signal generation aligned to RxCLK OUT falling edge, enabling sub-microsecond dimming control window. Use Value: Eliminates timing uncertainty in backlight modulation by deriving DE directly from recovered pixel clock domain. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD Link receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF364AMTD/NOPB | Same silicon die and electrical specs; differs only in packaging - tube format (38 pcs) vs. tape-and-reel (1000 pcs). | Identical functional use; selected for prototyping or low-volume builds where reel handling is unnecessary. | Choose DS90CF364AMTDX/NOPB for automated SMT production; DS90CF364AMTD/NOPB for bench validation or small-batch assembly. |
| SN65LVDS32 | Single-channel LVDS receiver (4-bit), no PLL, no parallel output - requires external logic to reconstruct FPD Link timing. | Not a functional replacement; used only in custom serializer/deserializer subsystems where full FPD Link compliance is not required. | Select SN65LVDS32 only if designing a non-standard LVDS-to-parallel bridge with FPGA-based timing recovery and no need for integrated PLL/strobe. |
Compared with DS90CF364AMTDX/NOPB, DS90CF364AMTD/NOPB offers identical performance in tube packaging for flexibility in early-stage development, while SN65LVDS32 lacks FPD Link protocol awareness, PLL, and parallel output - making it unsuitable as a drop-in alternative but viable for highly customized LVDS interface layering.
Availability
DS90CF364AMTDX/NOPB is available at Aetrix Electronics and suitable for industrial HMIs, embedded display modules, and automotive instrument clusters requiring stable component supply, long-term manufacturability, and RoHS-compliant TSSOP packaging.
Supply support for DS90CF364AMTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in high-reliability interface solutions.
The DS90CF364AMTDX/NOPB belongs to TI's Flat Panel Display Link product line, engineered specifically to replace bulky parallel TTL interfaces in LCD timing applications while maintaining signal integrity, timing precision, and power efficiency across VGA–SXGA resolutions.
FAQ
What is the maximum supported pixel clock frequency for DS90CF364AMTDX/NOPB?
The DS90CF364AMTDX/NOPB supports shift clock frequencies from 20 MHz to 65 MHz. At 65 MHz, it delivers full 18-bit RGB + control bandwidth (170 MB/s), enabling SXGA resolution at 60 Hz with dual-pixel mapping. Operation above 65 MHz is not characterized or guaranteed per the official datasheet.
Does DS90CF364AMTDX/NOPB require external components for PLL operation?
No. The DS90CF364AMTDX/NOPB integrates a complete PLL with on-chip VCO and loop filter. No external capacitors, resistors, or crystals are needed - simplifying layout and improving reliability compared to discrete PLL implementations.
How does the power-down mode affect DS90CF364AMTDX/NOPB outputs?
When PWR DOWN is asserted low, DS90CF364AMTDX/NOPB drives all 21 RxOUT pins low and disables RxCLK OUT. Output states remain low during power-down, and supply current drops to ≤55 µA. Recovery to active operation takes ≤10 ms after PWR DOWN is deasserted.
Can DS90CF364AMTDX/NOPB interface directly with a rising-edge strobe transmitter like DS90C383A?
Yes. The DS90CF364AMTDX/NOPB is explicitly designed to interoperate with both rising-edge (e.g., DS90C383A) and falling-edge (e.g., DS90C363A) transmitters without external logic. Its internal timing architecture accommodates either edge polarity for seamless system integration.
What is the meaning of "FPLINE, FPFRAME, DRDY" in the DS90CF364AMTDX/NOPB output mapping?
In DS90CF364AMTDX/NOPB, FPLINE corresponds to HSYNC, FPFRAME to VSYNC, and DRDY to Data Enable (DE). These three control signals are mapped to RxOUT[18], RxOUT[19], and RxOUT[20] respectively - providing full frame synchronization for LCD timing controllers without additional glue logic.
DS90CF364AMTDX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF364AMTDX/NOPB FAQ
1.How can I place an order for DS90CF364AMTDX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF364AMTDX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF364AMTDX/NOPB reliable?
The price and inventory of DS90CF364AMTDX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF364AMTDX/NOPB is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF364AMTDX/NOPB transactions.
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DS90CF364AMTDX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF364AMTDX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF364AMTDX/NOPB?
For technical support, including DS90CF364AMTDX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF364AMTDX/NOPB requirements.
6.How does Aetrix verify that DS90CF364AMTDX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF364AMTDX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF364AMTDX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF364AMTDX/NOPB?
All DS90CF364AMTDX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF364AMTDX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF364AMTDX/NOPB part is unused and in its original packaging.
Return procedure for DS90CF364AMTDX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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