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Texas Instruments DS90CF364MTD/NOPB
- Part No.:
- DS90CF364MTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CF364MTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:269
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Product details
Overview
DS90CF364MTD/NOPB from Texas Instruments is an 18-bit LVDS receiver for Flat Panel Display (FPD) Link applications, converting three LVDS data streams and one LVDS clock into 21-bit CMOS/TTL output (18 RGB + 3 control). It operates at up to 65 MHz shift clock frequency, delivers 170 MB/s throughput, supports falling-edge strobe timing, and targets XGA (1024×768) display interfaces in industrial and embedded display systems.
For engineers reviewing the DS90CF364MTD/NOPB datasheet, DS90CF364MTD/NOPB pinout, DS90CF364MTD/NOPB application, or DS90CF364MTD/NOPB equivalent, this page provides verified technical context, validated pin functions, real-world display interface use cases, and confirmed alternative parts with documented functional alignment and known trade-offs in strobe edge behavior and power consumption.
Technical Context
The DS90CF364MTD/NOPB implements a dedicated PLL-based LVDS receiver architecture synchronized to an incoming differential clock (RxCLK IN±), recovering 21-bit parallel TTL outputs with precise internal sampling windows defined by RSPos timing parameters (e.g., RSPos0 = 0.7–1.4 ns at 65 MHz). Its falling-edge strobe operation is fixed-no programmability-and requires matching with a falling-edge transmitter like DS90C363 or compatible legacy FPD Link sources.
It integrates separate power domains: LVDS VCC/GND for input receivers, PLL VCC/GND for clock recovery, and VCC/GND for TTL output drivers. Power-down mode (PWR DWN low) forces all 21 outputs low while drawing only 10–55 µA, enabling dynamic link management in portable or energy-sensitive displays.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Single 3.3 V rail required; no level-shifting needed for modern 3.3 V graphics controllers. |
| Data Rate | Up to 1.3 Gbps aggregate - Enables 65 MHz × 21 bits = 170 MB/s bandwidth for XGA resolution at 60 Hz with blanking. |
| Input Standard | TIA/EIA-644 LVDS compliant - Ensures interoperability with standard LVDS transmitters and noise-immune cable runs up to several meters. |
| Output Interface | 21-bit CMOS/TTL - Direct connection to FPGA, ASIC, or display timing controller without external buffers. |
| Strobe Edge | Falling-edge only - Fixed internal sampling aligned to RxCLK OUT falling edge; no configuration pin or register control. |
| Power Consumption | 43–60 mA typical at 65 MHz (16-grayscale pattern) - Enables chipset-level <250 mW operation when paired with DS90C363. |
| Operating Temperature | −40°C to +85°C - Qualified for industrial-grade display modules in automotive dashboards, medical monitors, and ruggedized HMI. |
Pinout & Package
DS90CF364MTD/NOPB uses a 48-pin TSSOP package (JEDEC MO-153, TI package code DGG), 12.6 mm × 6.1 mm body, 1.2 mm max height, with gull-wing leads and 0.5 mm pitch. Pin 1 located at top-left corner with molded dot marking; Q1 quadrant orientation in tape-and-reel packaging.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN+ / RxIN− (×3) | LVDS differential data inputs | Three 100 Ω-terminated pairs accepting LVDS data channels; require external 100 Ω differential termination at source or receiver end. |
| RxCLK IN+ / RxCLK IN− | LVDS differential clock input | Accepts recovered clock from DS90C363 TxCLK OUT±; drives internal PLL for data recovery and RxCLK OUT generation. |
| RxOUT0–RxOUT20 | CMOS/TTL parallel outputs | 21-bit bus: R0–R5, G0–G5, B0–B5, FPLINE (HSYNC), FPFRAME (VSYNC), DRDY (Data Enable); 3.3 V tolerant, 2 mA drive capability. |
| FPSHIFT OUT | TTL clock output | Falling-edge strobe signal (RxCLK OUT); used as data latch reference for downstream display controller; matches DS90C363 TxCLK IN timing. |
| PWR DWN | Active-low power-down control | Drives all RxOUT pins low and disables PLL when pulled low; draws ≤55 µA in shutdown-critical for display blanking or sleep modes. |
| VCC / GND (×4 / ×5) | Power and ground distribution | Dedicated VCC/GND sets per domain: TTL I/O (4×VCC/5×GND), LVDS inputs (1×LVDS VCC/3×LVDS GND), PLL (1×PLL VCC/2×PLL GND). |
Key Features
| Feature | Design Value |
|---|---|
| Falling-edge strobe receiver | Fixed internal sampling aligned to RxCLK OUT falling edge-eliminates need for external strobe inversion logic when paired with DS90C363. |
| Low EMI LVDS interface | 290 mV differential swing meets TIA/EIA-644; enables narrow twisted-pair cabling and reduces radiated emissions in display interconnects. |
| Integrated PLL with no external components | On-chip loop filter and VCO eliminate external capacitors or resistors-reduces BOM count and layout area in space-constrained display modules. |
| ESD-hardened inputs | >7 kV HBM rating on all LVDS and TTL pins-enhances robustness during handling and operation in unshielded industrial environments. |
| Power-down mode with zero-output state | PWR DWN assertion forces all 21 outputs low and cuts supply current to <55 µA-enables seamless display blanking without bus contention. |
Applications
| Industrial LCD Controller Interface | Medical Imaging Display Module |
|---|---|
Use Scenario: Connecting an FPGA-based timing controller to a 1024×768 TFT panel via flexible flat cable in a factory automation HMI. IC Role / Device Role / Timing Role: Receives serialized RGB/control data over three LVDS pairs and clock; reconstructs parallel 21-bit TTL bus synchronized to falling-edge strobe for pixel latching. Use Value: Replaces wide 21-bit TTL ribbon cable with 4 differential pairs-reducing EMI, connector size, and routing complexity while maintaining XGA timing integrity. |
Use Scenario: Driving high-reliability monochrome LCD in portable ultrasound equipment requiring stable grayscale rendering and low-power standby. IC Role / Device Role / Timing Role: LVDS-to-TTL bridge in imaging data path; recovers pixel data from graphics processor and asserts DRDY/HSYNC/VSYNC for frame synchronization. Use Value: −40°C to +85°C operation and <55 µA power-down current enable cold-start capability and battery-efficient idle states without display ghosting. |
| Automotive Instrument Cluster | Avionics Multi-Function Display |
Use Scenario: Transmitting rendered graphics from SoC to analog-digital hybrid cluster display with strict EMC requirements. IC Role / Device Role / Timing Role: Final stage in display pipeline-converts LVDS stream into TTL signals for column/row driver ICs; uses FPSHIFT OUT as system-wide latch reference. Use Value: 290 mV LVDS swing and 7 kV ESD rating ensure compliance with automotive ISO 10605 and reduce susceptibility to ignition noise in dashboard harnesses. |
Use Scenario: Integrating certified display subsystem into DO-254-compliant cockpit display unit with deterministic timing and fault containment. IC Role / Device Role / Timing Role: Safety-critical LVDS receiver providing traceable pixel data recovery; PWR DWN enables controlled black-screen transition during mode switching. Use Value: Guaranteed skew margin (RSKM = 400 ps at 65 MHz) accommodates cable length variation and jitter-supporting DO-160E lightning-induced transient resilience. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF564MTD/NOPB | 5 V supply, non-programmable falling-edge receiver; higher power (≈120 mA at 65 MHz), larger 56-pin TSSOP package. | Legacy 5 V systems only; incompatible with 3.3 V logic without level shifters; not drop-in replaceable due to voltage and pinout mismatch. | Select only for brownfield 5 V FPD Link upgrades where board redesign is impractical and 5 V rail remains available. |
| SN65LVDS32PW | Single-channel LVDS receiver (4-bit), no integrated PLL, no FPD Link-specific timing or 21-bit output bus. | Requires external clock recovery and parallelization logic; unsuitable for direct FPD Link replacement without significant FPGA glue logic. | Use only for custom LVDS deserialization where full FPD Link protocol handling is implemented externally. |
Compared with DS90CF364MTD/NOPB, DS90CF564MTD/NOPB demands 5 V infrastructure and increases power and board area, while SN65LVDS32PW lacks native FPD Link framing and forces system-level timing reconstruction-making DS90CF364MTD/NOPB the sole optimized solution for drop-in 3.3 V XGA display links.
Availability
DS90CF364MTD/NOPB is available at Aetrix Electronics and suitable for industrial HMI, medical imaging displays, automotive instrument clusters, and avionics MFDs requiring stable component supply across extended product lifecycles.
Supply support for DS90CF364MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in display interface solutions and industrial-grade reliability.
DS90CF364MTD/NOPB belongs to TI's FPD Link chipset family, engineered specifically to replace wide parallel TTL interfaces in flat-panel displays with noise-immune, high-speed LVDS serial links-targeting cost, EMI, and cable-size reduction in XGA and higher-resolution systems.
FAQ
What is the primary function of DS90CF364MTD/NOPB in a display system?
The DS90CF364MTD/NOPB serves as an 18-bit LVDS receiver that converts three LVDS data streams and one LVDS clock into a 21-bit parallel CMOS/TTL output bus (18 RGB + 3 control signals). It is designed specifically for Flat Panel Display (FPD) Link applications, enabling high-speed, low-EMI transmission between graphics controllers and display panels. DS90CF364MTD/NOPB operates with a fixed falling-edge strobe and supports up to 65 MHz clock rates for XGA resolution.
Does DS90CF364MTD/NOPB support rising-edge strobe operation?
No, DS90CF364MTD/NOPB is a fixed falling-edge strobe receiver and does not support rising-edge strobe configuration. Its FPSHIFT OUT (RxCLK OUT) signal and internal sampling window are hardwired to align with the falling edge of the recovered clock. To interface with a rising-edge transmitter, external strobe inversion or a compatible rising-edge receiver such as DS90C364 would be required. DS90CF364MTD/NOPB must be paired with a falling-edge transmitter like DS90C363 for proper operation.
What package type and pin count does DS90CF364MTD/NOPB use?
DS90CF364MTD/NOPB uses a 48-pin TSSOP package (JEDEC MO-153, TI package code DGG), measuring 12.6 mm × 6.1 mm with 0.5 mm lead pitch and 1.2 mm maximum height. Pin 1 is marked with a molded dot in the top-left corner, and the device follows Q1 quadrant orientation in tape-and-reel packaging. This compact, surface-mount package supports high-density PCB layouts common in display module designs.
Can DS90CF364MTD/NOPB operate with a 5 V supply?
No, DS90CF364MTD/NOPB is strictly a 3.3 V device with absolute maximum supply voltage of +4 V and recommended operating range of 3.0–3.6 V. It is not 5 V tolerant on any pin-including VCC, LVDS VCC, or PLL VCC-and applying 5 V will cause permanent damage. For 5 V systems, the pin-compatible but voltage-different DS90CF564MTD/NOPB should be used instead. DS90CF364MTD/NOPB requires clean, regulated 3.3 V rails for all three power domains.
How does the power-down mode work on DS90CF364MTD/NOPB?
When the PWR DWN pin is driven low, DS90CF364MTD/NOPB enters power-down mode: all 21 RxOUT pins are forced low, the internal PLL is disabled, and total supply current drops to 10–55 µA. Outputs remain in a defined low state-no floating or high-impedance behavior-ensuring bus stability during display blanking or sleep. Recovery time after PWR DWN release is ≤1 µs (RPDD), allowing rapid reactivation without display artifacts. DS90CF364MTD/NOPB maintains this behavior across its full −40°C to +85°C operating range.
DS90CF364MTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF364MTD/NOPB FAQ
1.How can I place an order for DS90CF364MTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF364MTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF364MTD/NOPB reliable?
The price and inventory of DS90CF364MTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF364MTD/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CF364MTD/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF364MTD/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CF364MTD/NOPB?
DS90CF364MTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF364MTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF364MTD/NOPB?
For technical support, including DS90CF364MTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF364MTD/NOPB requirements.
6.How does Aetrix verify that DS90CF364MTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF364MTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF364MTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF364MTD/NOPB?
All DS90CF364MTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF364MTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF364MTD/NOPB part is unused and in its original packaging.
Return procedure for DS90CF364MTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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