Texas Instruments DS90CF364MTDX/NOPB

Overview

DS90CF364MTDX/NOPB from Texas Instruments is an 18-bit LVDS receiver for flat-panel display (FPD) Link applications, converting three LVDS data streams and one LVDS clock into 21-bit CMOS/TTL output (18 RGB + 3 control signals). It operates at up to 65 MHz shift clock frequency, delivers 170 MB/s throughput, supports falling-edge strobe timing, and functions across −40°C to +85°C.

For engineers reviewing the DS90CF364MTDX/NOPB datasheet, DS90CF364MTDX/NOPB pinout, DS90CF364MTDX/NOPB application, or DS90CF364MTDX/NOPB equivalent, this page provides verified technical context, real-world timing behavior, package-validated pin roles, FPD Link interoperability details, and direct alternative options for display interface design.

Technical Context

The DS90CF364MTDX/NOPB implements a dedicated PLL-based LVDS-to-CMOS/TTL conversion architecture with internal skew margin management. It accepts differential LVDS inputs (RxIN± ×3 data lanes + RxCLK IN±), recovers embedded clock timing, and outputs synchronized TTL-level RGB/control signals with programmable falling-edge strobe (FPSHIFT OUT).

Its receiver PLL locks within 10 ms and maintains ±400 ps skew margin at 65 MHz, accommodating interconnect skew, ISI, and <250 ps cycle-to-cycle jitter. Power-down mode reduces supply current to ≤55 µA while holding outputs low - critical for dynamic panel power gating.

Key Specifications

Pinout & Package

DS90CF364MTDX/NOPB uses a 48-pin TSSOP (DGG) package, 12.4–12.6 mm × 6.0–6.2 mm × 1.2 mm max height, RoHS-compliant with Sn lead finish and MSL Level-2 rating.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS-to-TTL display interface applications.

Compared with DS90CF564MTD/NOPB, DS90CF364MTDX/NOPB enables lower-power 3.3 V operation and strobe flexibility; compared with SN65LVDS32PW, it delivers full FPD Link functionality including clock recovery, 21-bit deserialization, and display-timed strobe output - making it irreplaceable in XGA+ panel interfaces.

Availability

DS90CF364MTDX/NOPB is available at Aetrix Electronics and suitable for LCD panel interfaces, industrial HMIs, automotive infotainment systems, and embedded projector designs requiring stable component supply and long-term lifecycle support.

Supply support for DS90CF364MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in display interface solutions.

The DS90CF364MTDX/NOPB belongs to TI's Flat Panel Display Link chipset family, designed specifically to replace wide parallel TTL buses in high-resolution LCD applications with noise-immune, low-power LVDS serialization.

FAQ

What is the primary function of DS90CF364MTDX/NOPB in an FPD Link system?

The DS90CF364MTDX/NOPB serves as the LVDS receiver in a two-chip FPD Link solution, converting three differential LVDS data streams and one differential LVDS clock into 21-bit parallel CMOS/TTL outputs (18 RGB + 3 control signals). It recovers timing via an integrated PLL and delivers a falling-edge FPSHIFT OUT signal synchronized to the recovered data - enabling precise pixel latching in flat-panel displays. DS90CF364MTDX/NOPB is not a standalone serializer/deserializer but part of a matched transmitter-receiver pair with DS90C363.

Does DS90CF364MTDX/NOPB support rising-edge strobe output?

No, DS90CF364MTDX/NOPB is fixed to generate a falling-edge strobe on the FPSHIFT OUT pin, as confirmed by its pin description and truth table in the official datasheet. The rising/falling strobe selection is implemented only on the companion transmitter DS90C363 via the R_FB pin. DS90CF364MTDX/NOPB is designed to interoperate with both rising- and falling-edge transmitters without modification, but its own output strobe edge is not programmable. This ensures deterministic timing alignment for display controllers expecting falling-edge sampling.

What is the maximum supported pixel clock frequency for DS90CF364MTDX/NOPB?

DS90CF364MTDX/NOPB supports a maximum shift clock frequency of 65 MHz, as specified in the "Features" section and verified across AC timing parameters (e.g., RCOP, RCOH, RCOL). At this rate, it achieves 170 MB/s throughput and full XGA (1024×768) resolution with single-pixel-per-clock timing. Operation beyond 65 MHz is not characterized or guaranteed - setup/hold margins, PLL stability, and skew margin degrade outside the validated range. DS90CF364MTDX/NOPB is not rated for SXGA or UXGA resolutions requiring >65 MHz clocks.

How does DS90CF364MTDX/NOPB handle power-down mode?

When the PWR DWN pin is driven low, DS90CF364MTDX/NOPB enters power-down mode, reducing supply current to ≤55 µA and forcing all 21 RxOUT pins to logic low. Outputs remain in this state until PWR DWN is deasserted; the PLL relocks in ≤10 ms. This behavior is explicitly defined in the Electrical Characteristics table (ICCRZ parameter) and timing diagram Figure 19. DS90CF364MTDX/NOPB does not tri-state outputs in power-down - unlike the transmitter DS90C363 - making it suitable for systems where display data lines must be held low during sleep to prevent panel ghosting or leakage currents.

Is DS90CF364MTDX/NOPB pin-compatible with DS90CF564MTD/NOPB?

Yes, DS90CF364MTDX/NOPB is pin-compatible with DS90CF564MTD/NOPB: both use the same 48-pin TSSOP (DGG) package and share identical pin numbering, signal names, and I/O assignments per the datasheet pin diagrams (Figure 24) and descriptions. However, DS90CF364MTDX/NOPB operates at 3.3 V and includes updated internal circuitry for lower power and improved noise immunity, while DS90CF564MTD/NOPB requires 5 V. Direct replacement is possible only if the host board's power rails and signal levels are updated accordingly - the pinout match simplifies migration but does not eliminate voltage-level redesign.