Texas Instruments DS90CF366MTDX/NOPB

Overview

DS90CF366MTDX/NOPB from Texas Instruments is a 21-bit LVDS-to-LVCMOS deserializer receiver for flat-panel display (FPD) links, converting three LVDS data streams and one LVDS clock into 18-bit RGB + HSYNC/VSYNC/DE parallel outputs. It operates at 20–85 MHz clock rates, delivers 1.785 Gbps throughput, consumes <142 mW typical at 85 MHz grayscale, and supports VGA/SVGA/XGA displays in embedded video interfaces.

For engineers reviewing the DS90CF366MTDX/NOPB datasheet, DS90CF366MTDX/NOPB pinout, DS90CF366MTDX/NOPB application, or DS90CF366MTDX/NOPB equivalent, key selection criteria include LVDS input termination (100 Ω), falling-edge strobed RxCLKOUT timing, PWR_DWN-controlled power-down mode (<400 µA), and compatibility with TIA/EIA-644 LVDS standard in 48-pin TSSOP packaging.

Technical Context

The DS90CF366MTDX/NOPB implements a fully integrated PLL to recover 20–85 MHz LVDS clock signals without external components, enabling precise sampling of three serialized LVDS data lanes. Its internal serial-to-parallel converter reconstructs 21-bit LVCMOS output (18 RGB + 3 control) synchronized to the falling edge of RxCLKOUT.

It features dedicated LVDS input termination support (100 Ω differential), separate LVDS_VCC/LVDS_GND and PLL_VCC/PLL_GND supply domains, and failsafe bias circuitry that maintains high-impedance LVDS inputs during power transitions-preventing latch-up and ensuring robust operation in GPU-to-display interconnects.

Key Specifications

Pinout & Package

DS90CF366MTDX/NOPB is housed in a 48-pin TSSOP package (DGG), body size 12.50 mm × 6.10 mm, with exposed thermal pad not connected internally. Pin functions are validated per TI SNLS055J Rev J datasheet (pp. 3–6).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CF366MTDX/NOPB, DS90CF386MTDX/NOPB adds 7-bit deserialization capacity and supports higher-resolution displays, while SN65LVDS32DR lacks PLL and serialization logic entirely-making it unsuitable as a functional substitute for FPD-Link receiver applications.

Availability

DS90CF366MTDX/NOPB is available at Aetrix Electronics and suitable for embedded LCD display interfaces, industrial panel PCs, and machine vision camera links requiring stable component supply and long-term production continuity.

Supply support for DS90CF366MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS90CF366MTDX/NOPB belongs to TI's FPD-Link I family-designed specifically for cost-sensitive, low-power flat-panel display interconnects in consumer, industrial, and medical imaging equipment.

FAQ

What is the primary function of the DS90CF366MTDX/NOPB in a display system?

The DS90CF366MTDX/NOPB serves as an LVDS deserializer receiver that converts three serialized LVDS data lanes and one LVDS clock into 21-bit parallel LVCMOS output (18-bit RGB + HSYNC/VSYNC/DE). It is used between graphics processors and flat-panel displays to replace wide parallel buses with compact, low-EMI LVDS cabling. The DS90CF366MTDX/NOPB enables reliable transmission up to 85 MHz pixel clock rates in applications like industrial HMIs and medical displays.

Does the DS90CF366MTDX/NOPB require external components for PLL operation?

No, the DS90CF366MTDX/NOPB integrates a fully self-contained PLL that locks to the incoming LVDS clock (20–85 MHz) without any external capacitors, resistors, or crystal references. This simplifies design and reduces bill-of-materials cost. The DS90CF366MTDX/NOPB does require proper 100 Ω differential termination on each LVDS input pair and separate bypassing for VCC, LVDS_VCC, and PLL_VCC rails to maintain jitter performance.

How does the PWR_DWN pin affect DS90CF366MTDX/NOPB operation?

When the PWR_DWN pin is driven low, the DS90CF366MTDX/NOPB enters power-down mode, reducing supply current to less than 400 µA while forcing all 21 RxOUT signals low. This feature supports dynamic power management during display blanking or system sleep. The DS90CF366MTDX/NOPB resumes normal operation within 1 µs after PWR_DWN is released high, with PLL relock time of approximately 10 ms.

What are the supply voltage requirements for DS90CF366MTDX/NOPB?

The DS90CF366MTDX/NOPB requires three independent 3.3 V supplies: VCC (for LVCMOS I/O), LVDS_VCC (for LVDS receivers), and PLL_VCC (for PLL core). All must be regulated between 3.0 V and 3.6 V. Each supply must be decoupled with ≥0.1 µF ceramic capacitors placed near respective pins. The DS90CF366MTDX/NOPB specifies 100 mVPP maximum supply noise to ensure stable PLL operation and low-jitter RxCLKOUT generation.

Can DS90CF366MTDX/NOPB interface directly with standard LVCMOS display controllers?

Yes, the DS90CF366MTDX/NOPB outputs 21 LVCMOS signals (RxOUT[20:0]) compatible with 3.3 V logic families, including standard display timing controllers. Its RxCLKOUT pin provides a falling-edge strobe synchronized to the recovered clock-eliminating need for external clock inversion or translation logic. The DS90CF366MTDX/NOPB has been validated for direct connection to controllers supporting 18-bit RGB + DE/HSYNC/VSYNC timing, such as those found in ARM-based HMI platforms.