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Texas Instruments DS90CF383MTD/NOPB
- Part No.:
- DS90CF383MTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 56-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CF383MTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 56TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,207
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Product details
Overview
DS90CF383MTD/NOPB from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS transmitter IC for 24-bit flat panel display (FPD) link applications, converting 28-bit CMOS/TTL data (24 RGB + 3 control) into four LVDS data streams and one LVDS clock at up to 65 MHz, delivering 227 MB/s throughput and 1.8 Gbps aggregate bandwidth for XGA (1024×768) displays.
For engineers reviewing the DS90CF383MTD/NOPB datasheet, DS90CF383MTD/NOPB pinout, DS90CF383MTD/NOPB application, or DS90CF383MTD/NOPB equivalent, key selection considerations include its 56-pin TSSOP package, falling-edge strobe timing, 290 mV LVDS differential swing, −40°C to +85°C operating range, and compatibility with TIA/EIA-644 LVDS standard in high-noise display interconnects.
Technical Context
The DS90CF383MTD/NOPB implements a PLL-based transmit clock generator with no external components required, synchronizing 28-bit parallel input sampling to a falling-edge TxCLK IN strobe. It supports shift clock frequencies from 20 MHz to 65 MHz and delivers precisely timed LVDS outputs with channel-to-channel skew ≤250 ps and pulse position accuracy within ±0.4 ps to ±11.3 ns across bit lanes.
It features integrated power-down mode (<0.5 mW total), separate supply domains (VCC for TTL inputs, PLL VCC, LVDS VCC), and robust ESD protection (>7 kV HBM). Its TRI-STATE® outputs disable under PWR DOWN assertion, enabling hot-swap capability and system-level power gating in FPD link transmitter chains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Enables direct integration with 3.3V logic rails without level-shifting. |
| Data Rate per LVDS Channel | 455 Mbps - Supports 24-bit RGB + 3 control bits at 65 MHz pixel clock. |
| Differential Output Voltage (VOD) | 250–450 mV - Ensures low EMI and noise margin compliance with TIA/EIA-644. |
| Channel-to-Channel Skew | ≤250 ps - Maintains timing integrity across all four LVDS data lanes for pixel-aligned transmission. |
| Operating Temperature Range | −40°C to +85°C - Qualified for industrial and extended-temperature display subsystems. |
| Power-Down Current | 10–55 µA - Enables ultra-low standby power in portable or energy-sensitive FPD systems. |
| Input Clamp Voltage | −1.5 V - Protects against negative transients on CMOS/TTL inputs during hot insertion. |
Pinout & Package
DS90CF383MTD/NOPB is housed in a 56-lead molded thin shrink small outline package (TSSOP), JEDEC-compliant, with 0.5 mm lead pitch and moisture sensitivity level MSL-2 (260°C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TxIN[0:27] | CMOS/TTL Input | 28-bit parallel interface: 8R/8G/8B + FPLINE/FPFRAME/DRDY - sampled on falling edge of TxCLK IN. |
| TxOUT+[0:3], TxOUT−[0:3] | LVDS Differential Output | Four 7-bit LVDS data channels (28 bits total); each pair carries time-multiplexed pixel/control data. |
| TxCLK OUT+, TxCLK OUT− | LVDS Differential Clock Output | Transmits phase-locked 65 MHz (max) clock in parallel with data for synchronous receiver recovery. |
| FPSHIFT IN (TxCLK IN) | CMOS/TTL Clock Input | Falling-edge strobe - defines sampling instant for all 28 TxIN bits per cycle. |
| PWR DOWN | CMOS/TTL Control Input | Active-low signal that places all LVDS outputs in high-impedance state and reduces ICC to µA range. |
| VCC, PLL VCC, LVDS VCC | Power Supply Inputs | Three isolated 3.3V domains: core logic, PLL, and LVDS drivers - minimize cross-coupling and optimize noise performance. |
| GND, PLL GND, LVDS GND | Ground Terminals | Four TTL GND, two PLL GND, three LVDS GND - enable star-grounding and reduce ground bounce in mixed-signal operation. |
Key Features
| Feature | Design Value |
|---|---|
| Single 3.3V supply operation | Eliminates need for dual-rail supplies and simplifies PCB power delivery for display interface designs. |
| Falling-edge data strobe | Enables precise setup/hold timing alignment with legacy FPD Link receivers and avoids metastability in high-speed sampling. |
| No external PLL components | Reduces BOM count and layout area while ensuring stable clock generation across temperature and voltage variations. |
| 290 mV LVDS output swing | Meets TIA/EIA-644 specification and minimizes radiated emissions in cable-driven display interconnects. |
| Chipset power <250 mW (typ) | Supports thermally constrained embedded display modules and fanless industrial panels. |
Applications
| Industrial LCD Panels | Medical Diagnostic Displays |
|---|---|
|
Use Scenario: High-reliability 1024×768 monochrome or color LCD in factory HMIs with long cable runs between controller and panel. IC Role / Device Role / Timing Role: FPD Link transmitter converting parallel RGB+control signals to noise-immune LVDS for EMI-resistant transmission over twisted-pair cables. Use Value: Replaces wide 28-bit TTL buses with 5 differential pairs, reducing connector size, crosstalk, and radiated emissions by >20 dB. |
Use Scenario: DICOM-compliant diagnostic monitor requiring stable pixel timing and zero frame drop across 24/7 operation. IC Role / Device Role / Timing Role: Timing-critical LVDS transmitter enforcing strict channel skew ≤250 ps and jitter-controlled clock distribution. Use Value: Guarantees pixel-perfect synchronization and eliminates visual artifacts caused by inter-lane timing misalignment. |
| Avionics Display Units | Test & Measurement Equipment |
|
Use Scenario: Ruggedized cockpit display with MIL-STD-810G environmental compliance and wide temperature operation. IC Role / Device Role / Timing Role: Robust LVDS transmitter supporting −40°C to +85°C operation and >7 kV HBM ESD protection on all I/O pins. Use Value: Ensures uninterrupted video transmission during thermal cycling, vibration, and electrostatic discharge events in flight systems. |
Use Scenario: Automated optical inspection (AOI) system requiring real-time image streaming from FPGA-based frame grabbers to LCD monitors. IC Role / Device Role / Timing Role: High-bandwidth bridge translating parallel camera sensor output to LVDS for low-latency display rendering. Use Value: Delivers 227 MB/s sustained throughput with deterministic latency (<5.5 ns clock delay), enabling sub-frame synchronization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS transmitter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LVDS386DGG | Same 56-pin TSSOP package, but supports up to 85 MHz clock and includes internal termination resistors. | Targets higher-resolution displays (SXGA+) and eliminates external 100Ω terminations on PCB. | Preferred when upgrading beyond XGA resolution or minimizing board space for termination networks. |
| DS90C385MTD | Pin-compatible successor with enhanced ESD rating (±15 kV HBM) and improved power-down current (≤1 µA). | Designed for next-gen industrial displays requiring extended lifecycle support and tighter power budgeting. | Recommended for new designs where long-term availability and lower standby power are critical. |
Compared with SN65LVDS386DGG and DS90C385MTD, DS90CF383MTD/NOPB offers proven XGA-optimized timing, minimal external component count, and broad legacy design compatibility-making it ideal for cost-sensitive, volume-manufactured display interfaces where 65 MHz bandwidth suffices.
Availability
DS90CF383MTD/NOPB is available at Aetrix Electronics and suitable for industrial LCD panels, medical diagnostic displays, avionics display units, and test & measurement equipment requiring stable component supply and long-term obsolescence management.
Supply support for DS90CF383MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments (TI) is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with deep heritage in interface ICs and display solutions.
The DS90CF383MTD/NOPB belongs to TI's legacy FPD Link family, engineered specifically to replace bulky TTL display buses with compact, low-EMI LVDS links for flat panel applications ranging from consumer to mission-critical systems.
FAQ
What is the maximum supported pixel clock frequency for DS90CF383MTD/NOPB?
The DS90CF383MTD/NOPB supports a maximum shift clock frequency of 65 MHz, enabling full XGA (1024×768) resolution at 60 Hz with 24-bit RGB and 3 control signals. At this rate, each LVDS data channel operates at 455 Mbps, yielding 227 MB/s aggregate throughput. Exceeding 65 MHz violates AC timing specifications including TCCS and TPPos limits.
Does DS90CF383MTD/NOPB require external components for PLL operation?
No, DS90CF383MTD/NOPB integrates a fully self-contained PLL with no external capacitors or resistors required. The PLL locks to the incoming TxCLK IN signal and generates the internal transmit clock used to serialize the 28-bit parallel input. This simplifies layout and improves reliability compared to discrete oscillator-based solutions.
How does the power-down mode function on DS90CF383MTD/NOPB?
Asserting the PWR DOWN pin low places all LVDS outputs (TxOUT±[0:3] and TxCLK OUT±) into high-impedance TRI-STATE® mode and reduces total supply current to 10–55 µA. This feature enables dynamic power gating in battery-powered or thermally constrained systems without disrupting upstream logic or requiring reset sequencing.
Is DS90CF383MTD/NOPB compatible with 5V TTL input levels?
No, DS90CF383MTD/NOPB accepts only 3.3V CMOS/TTL input levels (VIH = 2.0 V min, VIL = 0.8 V max) and is not 5V tolerant. Driving it with 5V logic risks damage to input structures. For 5V system integration, level translation or use of the pin-compatible 5V predecessor DS90CF583 is required.
What package type and lead finish does DS90CF383MTD/NOPB use?
DS90CF383MTD/NOPB uses a 56-lead TSSOP (package code DGG, NS MTD56) with lead finish of matte tin (Sn), RoHS-compliant, and moisture sensitivity level MSL-2 (260°C peak reflow, 1-year floor life). It ships in tubes (34 pcs) or tape-and-reel (1000 pcs) formats.
DS90CF383MTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 56-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Not For New Designs
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 56-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF383MTD/NOPB FAQ
1.How can I place an order for DS90CF383MTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF383MTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF383MTD/NOPB reliable?
The price and inventory of DS90CF383MTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF383MTD/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CF383MTD/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF383MTD/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CF383MTD/NOPB?
DS90CF383MTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF383MTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF383MTD/NOPB?
For technical support, including DS90CF383MTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF383MTD/NOPB requirements.
6.How does Aetrix verify that DS90CF383MTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF383MTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF383MTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF383MTD/NOPB?
All DS90CF383MTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF383MTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF383MTD/NOPB part is unused and in its original packaging.
Return procedure for DS90CF383MTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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