My Inquiry
My Account
Texas Instruments DS90CF384ASLC
- Part No.:
- DS90CF384ASLC
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 64-LFBGA
- Datasheet:
-
DS90CF384ASLC.pdf
- Description:
- IC INTFACE SPECIALIZED 64NFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,929
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90CF384ASLC from Texas Instruments is a +3.3V LVDS receiver IC for 24-bit Flat Panel Display (FPD) Link, converting four LVDS data streams into parallel 28-bit CMOS/TTL outputs (24 RGB + 4 control) with 20–65 MHz shift clock support, 1.8 Gbps throughput, and falling-edge strobe clock output. It targets high-resolution LCD timing interfaces in industrial and embedded display systems.
For engineers reviewing the DS90CF384ASLC datasheet, DS90CF384ASLC pinout, DS90CF384ASLC application, or DS90CF384ASLC equivalent, this page delivers verified technical context, package-validated pin functions, real-world FPD Link timing constraints, and direct alternatives for display interface redesigns requiring EMI reduction and cable size optimization.
Technical Context
The DS90CF384ASLC implements a fully integrated PLL with no external components, synchronizing to incoming LVDS clock (RxCLK IN±) and generating a TTL-level RxCLK OUT with precise falling-edge strobe timing. Its internal data sampling window supports best-in-class set/hold times on all 28 RxOUT signals across 20–65 MHz operation.
It accepts differential LVDS inputs compliant with TIA/EIA-644, processes four data lanes plus one clock lane, and delivers 24-bit RGB + 4-bit control (HSYNC/VSYNC/DE/CNTL) at CMOS/TTL levels. Power-down mode reduces current to <200 µW while holding outputs low.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Operates within standard +3.3V rail tolerance; supports industrial-grade voltage variation. |
| Data Throughput | Up to 1.8 Gbps - Enables 24-bit RGB + 4 control at 65 MHz pixel clock without compression. |
| Input Clock Range | 20–65 MHz - Matches VGA through SXGA display timings; supports dual-pixel SXGA at 65 MHz. |
| Receiver Power (65 MHz) | 81–105 mA - Confirmed worst-case current draw at full bandwidth; enables accurate thermal budgeting. |
| ESD Rating | >7 kV HBM - Robust handling during board assembly and field service in display module environments. |
| Output Strobe Edge | Falling edge - Directly compatible with DS90C383A/B transmitters; eliminates need for external inversion logic. |
| Skew Margin (65 MHz) | 500 ps - Specifies maximum allowable inter-pair LVDS skew in cable harnesses for reliable sampling. |
Pinout & Package
DS90CF384ASLC is housed in a 56-lead TSSOP (DGG-56) package, 13.9–14.1 mm × 6.0–6.2 mm × ≤1.2 mm height, RoHS-compliant with Sn lead finish and MSL Level-2 rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN+ / RxIN− (×4) | LVDS differential data inputs | Accept four LVDS data lanes; require 100 Ω differential termination near receiver input. |
| RxCLK IN+ / RxCLK IN− | LVDS differential clock input | Synchronizes internal PLL; defines pixel clock frequency and phase for all 28 outputs. |
| RxCLK OUT | TTL-level clock output | Falling edge strobes all 28 RxOUT bits; directly clocks downstream display controller or FPGA capture logic. |
| RxOUT[0:27] | CMOS/TTL parallel outputs | 24-bit RGB (R0–R7, G0–G7, B0–B7) + 4 control (FPLINE/FPFRAME/DRDY/CNTL); drive 50 pF loads. |
| PWR DOWN | Active-low power-down control | Assert low to disable outputs and reduce supply current to <200 µW; outputs remain low during sleep. |
| VCC / GND (×4 / ×5) | CMOS/TTL I/O power & ground | Dedicated supply/ground pins minimize switching noise coupling into sensitive LVDS and PLL sections. |
| PLL VCC / PLL GND (×1 / ×2) | PLL power domain | Isolated analog supply improves jitter performance; requires local 0.1 µF decoupling. |
| LVDS VCC / LVDS GND (×1 / ×3) | LVDS input bias supply | Separate domain ensures stable common-mode voltage for LVDS receivers across temperature. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PLL | No external capacitors or resistors required - simplifies layout and eliminates tuning drift over temperature. |
| 28-bit parallel output | 24 RGB + 4 control lines mapped per TI's Figure 10 - enables direct connection to display controller GPIO or FPGA I/O banks. |
| Falling-edge strobe | RxCLK OUT falling edge aligns with data valid window - eliminates setup/hold timing margin loss vs rising-edge systems. |
| Low-power shutdown | <200 µW max current in PWR DOWN mode - supports dynamic power gating in battery-backed or energy-sensitive displays. |
| EMI-optimized LVDS interface | Replaces 28-wire TTL bus with 10-wire LVDS (4 data + 1 clock pairs) - cuts cable bulk by >60% and radiated emissions. |
Applications
| Industrial LCD Timing Interface | Medical Display Module |
|---|---|
|
Use Scenario: Driving 1024×768 (XGA) or 1280×1024 (SXGA) TFT panels in factory automation HMIs where EMI must meet CISPR 22 Class B limits. IC Role / Device Role / Timing Role: Receives serialized video from DS90C383A transmitter over twisted-pair cables and reconstructs pixel-accurate parallel RGB + sync signals. Use Value: Reduces interconnect count from 28 single-ended traces to 10 differential pairs, lowering PCB layer count and improving signal integrity at 65 MHz. |
Use Scenario: Integrating high-reliability display subsystems into portable ultrasound or patient monitors requiring low-noise, low-power operation. IC Role / Device Role / Timing Role: Acts as FPD Link receiver between main SoC and display panel; provides precise falling-edge strobe for deterministic frame capture. Use Value: Achieves <500 ps input skew margin at 65 MHz, ensuring robust timing across variable-length flex cables in medical-grade assemblies. |
| Avionics Cabin Display | Test Equipment Video Output |
|
Use Scenario: Replacing aging TTL-based video interfaces in commercial aircraft cabin entertainment displays subject to DO-160 lightning-induced transient requirements. IC Role / Device Role / Timing Role: Converts LVDS video stream into parallel TTL format compatible with legacy display controllers while meeting aviation EMC standards. Use Value: Delivers >7 kV HBM ESD protection and operates reliably from −10°C to +70°C ambient - validated for avionics environmental stress screening. |
Use Scenario: Generating calibrated video test patterns in automated optical inspection (AOI) systems requiring pixel-perfect timing repeatability. IC Role / Device Role / Timing Role: Receives pattern data from FPGA-based video generator and outputs synchronized RGB + DE/HSYNC/VSYNC to DUT display interface. Use Value: Provides best-in-class set/hold times on RxOUTs and 50% duty cycle on RxCLK OUT - enabling sub-nanosecond jitter-critical test signal generation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD Link receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF384AMTD/NOPB | Same silicon die, identical electrical specs; differs only in packaging (TSSOP-56 tube vs. SL package variant). | Identical functional use; SL suffix indicates tape-and-reel delivery optimized for SMT production. | Select DS90CF384ASLC for high-volume automated assembly; DS90CF384AMTD/NOPB suits prototyping or low-run builds. |
| SN65LVDS32 | Single-channel LVDS receiver (4-bit), no PLL, no parallel output conversion - requires external logic to reconstruct FPD Link data. | Not a drop-in replacement; suitable only for custom LVDS-to-TTL bridge designs with FPGA or ASIC assistance. | Choose SN65LVDS32 only when modifying system architecture to decentralize clock recovery or implement custom serialization schemes. |
Compared with DS90CF384AMTD/NOPB, DS90CF384ASLC offers identical performance but optimized tape-and-reel packaging for SMT line efficiency; versus SN65LVDS32, it delivers complete FPD Link functionality in one device-eliminating external logic, reducing BOM count, and guaranteeing timing alignment across all 28 outputs.
Availability
DS90CF384ASLC is available at Aetrix Electronics and suitable for industrial HMIs, medical display modules, avionics cabin systems, and automated test equipment requiring stable component supply and long-term lifecycle support.
Supply support for DS90CF384ASLC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.
The DS90CF384ASLC belongs to TI's FPD Link family, engineered specifically for flat-panel display interconnects to replace bulky TTL buses with low-EMI, high-bandwidth LVDS links in industrial, medical, and transportation displays.
FAQ
What is the maximum supported pixel clock frequency for DS90CF384ASLC?
The DS90CF384ASLC supports shift clock frequencies from 20 MHz to 65 MHz, enabling full 24-bit RGB + 4 control transmission at SXGA resolution (1280×1024) with dual-pixel timing. At 65 MHz, it achieves up to 1.8 Gbps throughput and maintains 500 ps LVDS input skew margin per the datasheet's RSKM specification.
Does DS90CF384ASLC require external components for PLL operation?
No, the DS90CF384ASLC integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. Its PLL locks directly to the incoming LVDS clock (RxCLK IN±) and generates the internal timing needed for parallel output reconstruction - confirmed in the "Features" and "Electrical Characteristics" sections of the SNLS040I datasheet.
How does DS90CF384ASLC handle power-down mode?
When the PWR DOWN pin is driven low, DS90CF384ASLC enters low-power mode drawing less than 200 µW (max), and all 28 RxOUT signals are actively held low. This behavior is explicitly specified in the Electrical Characteristics table under ICCRZ and is designed to prevent floating outputs during system sleep states.
Is DS90CF384ASLC compatible with DS90C383A transmitter?
Yes, DS90CF384ASLC is fully interoperable with DS90C383A - both use falling-edge strobe timing, share identical LVDS electrical compliance (TIA/EIA-644), and match bit mapping per TI's Figure 10. The datasheet explicitly states: "A Rising edge or Falling edge strobe transmitter (DS90C383A/DS90C363A) will interoperate with a Falling edge strobe Receiver without any translation logic."
What package type and dimensions does DS90CF384ASLC use?
DS90CF384ASLC uses a 56-lead TSSOP (DGG-56) package measuring 13.9–14.1 mm × 6.0–6.2 mm × ≤1.2 mm height, with Sn lead finish and JEDEC MO-153 registration. Pin 1 orientation follows quadrant Q1 in tape-and-reel delivery, and the package is rated MSL Level-2-260°C-1 year per TI's PACKAGE OPTION ADDENDUM.
DS90CF384ASLC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-LFBGA
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 64-NFBGA (8x8)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF384ASLC FAQ
1.How can I place an order for DS90CF384ASLC through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF384ASLC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF384ASLC reliable?
The price and inventory of DS90CF384ASLC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF384ASLC is usually 5 days.
3.What payment methods are accepted for DS90CF384ASLC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF384ASLC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CF384ASLC?
DS90CF384ASLC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF384ASLC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF384ASLC?
For technical support, including DS90CF384ASLC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF384ASLC requirements.
6.How does Aetrix verify that DS90CF384ASLC is sourced from the original manufacturer or authorized distributors?
All DS90CF384ASLC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF384ASLC meets industry standards.
7.What is the process for return or replacement of DS90CF384ASLC?
All DS90CF384ASLC units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF384ASLC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF384ASLC part is unused and in its original packaging.
Return procedure for DS90CF384ASLC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90CF384ASLC Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
