Texas Instruments DS90CF384MTDX/NOPB

Overview

DS90CF384MTDX/NOPB from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS receiver in the FPD-Link chipset, converting four LVDS data streams and one LVDS clock into 28-bit LVCMOS/LVTTL output (24-bit RGB + 3 control signals). It operates up to 65 MHz, delivers 227 MB/s throughput, supports falling-edge strobe timing, and is rated for −40°C to +85°C industrial temperature range. It enables high-resolution flat-panel display interconnects in space-constrained embedded displays.

For engineers reviewing the DS90CF384MTDX/NOPB datasheet, DS90CF384MTDX/NOPB pinout, DS90CF384MTDX/NOPB application, or DS90CF384MTDX/NOPB equivalent, key selection considerations include its TSSOP-56 package compatibility, LVDS-to-TTL level translation capability, power-down mode (<0.5 mW), 290 mV differential swing for EMI reduction, and interoperability with DS90C383/DS90C383MTDX/NOPB transmitters in XGA (1024×768) and higher-resolution display links.

Technical Context

The DS90CF384MTDX/NOPB implements a PLL-based LVDS receiver architecture that recovers clock and data from five differential LVDS inputs (four data pairs + one clock pair), then reconstructs synchronized 28-bit parallel TTL outputs with precise internal strobe positioning (e.g., RSPos0 = 0.7–1.4 ns at 65 MHz). Its falling-edge data strobe output (FPSHIFT OUT / RxCLK OUT) aligns with industry-standard FPD-Link timing conventions.

It features dedicated LVDS and TTL power domains (LVDS VCC, PLL VCC, VCC), independent ground planes (LVDS GND, PLL GND, GND), and a programmable power-down input (PWR DOWN) that forces outputs low while drawing <55 µA. The device complies with TIA/EIA-644 LVDS standards and provides >7 kV HBM ESD protection.

Key Specifications

Pinout & Package

DS90CF384MTDX/NOPB uses a 56-lead TSSOP (MTD56) package, 12.5 mm × 6.1 mm footprint, 0.5 mm lead pitch, RoHS-compliant matte tin (SN) finish, MSL Level-2 (260°C peak reflow).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS receiver applications.

Compared with DS90CF384MTD/NOPB, DS90CF384MTDX/NOPB offers identical performance in large tape-and-reel format (1000 pcs), simplifying high-volume SMT line feeding; versus SN65LVDS386D, it avoids added BOM cost and layout complexity of external strobe inversion while preserving timing alignment and EMI advantages of native falling-edge output.

Availability

DS90CF384MTDX/NOPB is available at Aetrix Electronics and suitable for embedded industrial displays, automotive infotainment systems, and medical diagnostic monitors requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for DS90CF384MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains full technical and supply chain continuity for legacy FPD-Link products including the DS90CF384 series.

This device belongs to TI's Flat Panel Display Link (FPD-Link) product line, engineered specifically to replace wide, high-speed TTL interfaces in display interconnects-reducing EMI, cable size, and PCB routing complexity while supporting XGA and higher resolutions.

FAQ

What is the function of the PWR DOWN pin on DS90CF384MTDX/NOPB?

The PWR DOWN pin is an active-low control input that places all 28 RxOUT signals in a low state and reduces total supply current to less than 55 µA when asserted. This feature enables rapid power gating during display blanking or system sleep states. DS90CF384MTDX/NOPB does not require external pull-up resistors on PWR DOWN, as internal circuitry ensures defined behavior during power-up and floating conditions.

Does DS90CF384MTDX/NOPB support both rising- and falling-edge strobe modes?

No-DS90CF384MTDX/NOPB is a fixed falling-edge strobe receiver. Its FPSHIFT OUT (RxCLK OUT) signal always asserts a falling edge aligned to recovered data sampling points (e.g., RSPos0 = 0.7–1.4 ns at 65 MHz). It is designed to interoperate with DS90C383/DS90C383MTDX/NOPB transmitters configured for either rising or falling edge, but DS90CF384MTDX/NOPB itself does not offer strobe polarity selection.

Can DS90CF384MTDX/NOPB be used with 5V-tolerant controllers?

No-DS90CF384MTDX/NOPB accepts only 3.3V LVDS inputs and delivers 3.3V LVCMOS/LVTTL outputs. Its LVDS inputs are not 5V tolerant, and its RxOUT pins are specified for VOH ≥2.7 V and VOL ≤0.3 V at 3.3V supply. Connecting to 5V logic without level translation risks damage or incorrect operation. DS90CF384MTDX/NOPB must be used in fully 3.3V systems or paired with appropriate level shifters.

What is the maximum supported pixel clock frequency for DS90CF384MTDX/NOPB?

DS90CF384MTDX/NOPB supports a maximum pixel clock frequency of 65 MHz, enabling single-pixel-per-clock timing for XGA (1024×768), SXGA (1280×1024), and higher-resolution displays. At this rate, each LVDS data channel carries 455 Mbps, achieving 227 MB/s aggregate throughput. Performance is guaranteed across the full −40°C to +85°C operating temperature range with 3.0–3.6 V supply.

How does DS90CF384MTDX/NOPB handle LVDS input skew and jitter?

DS90CF384MTDX/NOPB provides a 400 ps receiver skew margin (RSKM) at 65 MHz, accommodating interconnect skew (10–40 ps/ft), cycle-to-cycle jitter (<250 ps), and inter-symbol interference. This margin is derived from validated min/max pulse positions (e.g., RSPos0–RSPos6) and internal setup/hold windows. The integrated PLL locks within 10 ms and maintains stable recovery without external components, ensuring robust operation over varying cable lengths and noise environments.