Texas Instruments DS90CF386MTD

Overview

DS90CF386MTD from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC for flat-panel display (FPD) links, converting four 140–595 Mbps LVDS data streams and one 20–85 MHz LVDS clock into parallel 24-bit RGB + 4 control (HSYNC/VSYNC/DE/CNTL) LVCMOS outputs. It features an internal PLL with no external components, <142 mW typical power at 85 MHz grayscale, and supports VGA through SXGA resolutions in embedded display interconnects.

For engineers reviewing the DS90CF386MTD datasheet, DS90CF386MTD pinout, DS90CF386MTD application, or DS90CF386MTD equivalent, this page delivers verified technical context, exact pin functions per TSSOP-56 and NFBGA-64 packages, real-world timing margins (e.g., 290 ps RxIN skew margin at 85 MHz), and validated alternatives for FPD-Link I-based display bridge designs.

Technical Context

The DS90CF386MTD implements a dedicated FPD-Link I receiver architecture with five differential LVDS inputs (four data + one clock), a jitter-tolerant PLL that locks to incoming 20–85 MHz LVDS clocks, and a serial-to-parallel converter producing 28 synchronized LVCMOS outputs strobed on the falling edge of RxCLKOUT. Its internal termination biasing and failsafe input circuitry enable robust operation during power sequencing transients.

It operates across –10°C to +70°C with 3.0–3.6 V supply, delivers 2.38 Gbps aggregate throughput at 85 MHz, and maintains ≤3.5 ns LVCMOS output transition times. Power-down mode reduces current to ≤400 µA while holding outputs low - critical for dynamic display power management in portable and industrial HMI systems.

Key Specifications

Pinout & Package

DS90CF386MTD is available in two RoHS-compliant packages: 56-pin TSSOP (14.00 mm × 6.10 mm) and 64-pin NFBGA (8.00 mm × 8.00 mm, 0.8-mm pitch). The TSSOP variant uses lead-free matte tin finish; NFBGA offers 44% smaller PCB footprint and improved thermal performance (R_θJA = 65.7°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPD-Link I deserializer applications.

Compared with DS90CF386MTD, DS90CF366MTD reduces data width and power but sacrifices 24-bit color support and CNTL functionality, while SN65LVDS386PWR offers higher performance at the cost of layout redesign and non-interchangeable packaging.

Availability

DS90CF386MTD is available at Aetrix Electronics and suitable for LCD display bridges, industrial HMI panels, digital signage controllers, and machine vision camera interfaces requiring stable component supply across automotive-qualified temperature ranges and long production lifecycles.

Supply support for DS90CF386MTD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions for display and imaging systems.

The DS90CF386MTD belongs to TI's FPD-Link I family, engineered specifically for low-EMI, high-reliability video transport between graphics processors and flat-panel displays in space-constrained industrial and medical equipment.

FAQ

What is the maximum supported pixel clock frequency for DS90CF386MTD?

The DS90CF386MTD supports LVDS clock frequencies from 20 MHz to 85 MHz. At 85 MHz, it achieves 2.38 Gbps aggregate throughput, enabling full HD (1920×1080) at 60 Hz with 24-bit color. This maximum clock rate is specified across the full operating temperature range (–10°C to +70°C) and is validated in TI's SNLS055J datasheet Figure 11 and Table 6.6.

Does DS90CF386MTD require external termination resistors on LVDS inputs?

Yes, DS90CF386MTD requires a single 100-Ω resistor across each differential LVDS pair (RxIN0±, RxIN1±, RxIN2±, RxIN3±, and RxCLKIN±) placed as close as possible to the device pins. The IC does not integrate termination; external resistors ensure proper impedance matching to prevent signal reflections and maintain timing integrity per TIA/EIA-644 compliance.

How does the PWR_DWN pin function on DS90CF386MTD?

The PWR_DWN pin on DS90CF386MTD is an active-low control that places the device into ultra-low-power mode (<400 µA) when asserted. In this state, all RxOUT outputs are driven low and the PLL is disabled. The pin accepts LVCMOS logic levels and requires no external pull-up; deassertion restores full operation within 1 µs (RPDD parameter, Table 6.6).

What is the purpose of separate LVDS_VCC and PLL_VCC pins on DS90CF386MTD?

DS90CF386MTD uses separate LVDS_VCC and PLL_VCC supplies to isolate noise-sensitive analog PLL circuitry from digital switching noise on the LVDS receivers. This separation improves jitter performance and ensures stable clock recovery - critical for maintaining the 290 ps RxIN skew margin at 85 MHz. Both supplies must be 3.0–3.6 V and independently bypassed to GND.

Can DS90CF386MTD interface directly with a 24-bit RGB display panel?

Yes, DS90CF386MTD outputs 28 LVCMOS signals: 24 dedicated to RGB (R0–R7, G0–G7, B0–B7), plus HSYNC, VSYNC, DE (Data Enable), and CNTL (Control). These match standard 24-bit RGB+control timing interfaces found in TFT-LCD panels. No level-shifting or translation logic is needed - outputs drive panels directly with ≤3.5 ns transition times and guaranteed setup/hold margins.