Texas Instruments DS90CF386MTD/NOPB

Overview

DS90CF386MTD/NOPB from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC for flat-panel display (FPD) links, converting four 140–595 Mbps LVDS data streams and one 20–85 MHz LVDS clock into parallel 24-bit RGB + 4 control (HSYNC/VSYNC/DE/CNTL) LVCMOS outputs. It features an internal PLL with no external components, <142 mW typical power at 85 MHz grayscale, and supports VGA through single-pixel SXGA resolutions in embedded display interfaces.

For engineers reviewing the DS90CF386MTD/NOPB datasheet, DS90CF386MTD/NOPB pinout, DS90CF386MTD/NOPB application, or DS90CF386MTD/NOPB equivalent, key selection criteria include LVDS input termination (100 Ω differential), RxCLKOUT falling-edge strobe timing, PWR_DWN active-low power-down mode, and compatibility with TIA/EIA-644 LVDS standard for noise-immune video transport over cables or PCB traces.

Technical Context

The DS90CF386MTD/NOPB implements a dedicated FPD-Link I receiver architecture with five LVDS inputs (four data + one clock), a jitter-tolerant PLL for clock recovery, and a 7:1 deserialization ratio per LVDS lane-yielding 28 parallel LVCMOS outputs (RxOUT[27:0]). Its internal PLL locks to incoming LVDS clock frequencies from 20 MHz to 85 MHz, enabling stable sampling of serialized bitstreams where each bit occupies 1/7th of the clock period.

It operates at 3.3 V (3.0–3.6 V range), delivers LVCMOS outputs with 2.7 V VOH (IOH = –0.4 mA) and 0.3 V VOL (IOL = 2 mA), and supports precise timing with RxCLKOUT skew margin of 290 ps at 85 MHz. Power-down mode reduces supply current to ≤400 μA while holding outputs low.

Key Specifications

Pinout & Package

DS90CF386MTD/NOPB is available in a 56-pin TSSOP (DGG) package measuring 14.00 mm × 6.10 mm, with exposed thermal pad not electrically connected. Pin functions are validated per TI SNLS055J Rev J datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CF366MTD/NOPB, DS90CF386MTD/NOPB adds 7 extra data bits and a fourth LVDS lane to support 24-bit RGB; compared with SN65LVDS32PW, it integrates full clock recovery, deserialization, and strobe generation - eliminating FPGA or ASIC logic needed for FPD-Link I compliance.

Availability

DS90CF386MTD/NOPB is available at Aetrix Electronics and suitable for embedded LCD display interfaces, industrial panel PCs, Open LDI-to-RGB bridges, and digital projector video transport requiring stable component supply and long-term production continuity.

Supply support for DS90CF386MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in display interface solutions.

The DS90CF386MTD/NOPB belongs to TI's FPD-Link I family, designed specifically for cost-effective, low-EMI serialization of RGB video signals in flat-panel displays, industrial HMIs, and digital imaging systems.

FAQ

What is the primary function of the DS90CF386MTD/NOPB in a display system?

The DS90CF386MTD/NOPB is a 28-bit LVDS deserializer that converts four serialized LVDS data streams and one LVDS clock into parallel 24-bit RGB + 4 control (HSYNC/VSYNC/DE/CNTL) LVCMOS signals. In a display system, DS90CF386MTD/NOPB recovers timing and data from a high-speed serial link to drive TFT or LCD panels directly - replacing bulky parallel buses while maintaining pixel-accurate timing via its falling-edge RxCLKOUT strobe.

Does the DS90CF386MTD/NOPB require external components for PLL operation?

No, the DS90CF386MTD/NOPB integrates a complete PLL with no external components required. Its internal loop filter enables lock to LVDS clock frequencies from 20 MHz to 85 MHz without external capacitors or resistors - simplifying design, reducing BOM cost, and improving reliability versus discrete PLL implementations. This is explicitly confirmed in the TI SNLS055J datasheet Feature list and Section 7.3.2.

What are the valid supply voltage ranges for DS90CF386MTD/NOPB operation?

The DS90CF386MTD/NOPB operates with a nominal 3.3 V supply, specified over 3.0 V to 3.6 V (Recommended Operating Conditions, Section 6.3). Supply noise must remain below 100 mVPP. Exceeding 3.6 V risks permanent damage per Absolute Maximum Ratings (Section 6.1), and operation below 3.0 V may cause timing violations or output instability - both conditions invalidate functional operation per TI's datasheet specifications.

How does the PWR_DWN pin affect DS90CF386MTD/NOPB outputs during power-down mode?

When the PWR_DWN pin is asserted low, DS90CF386MTD/NOPB enters power-down mode: all 28 LVCMOS outputs (RxOUT[27:0]) are actively driven low, and supply current drops to ≤400 μA. Outputs remain low until PWR_DWN is deasserted high, at which point the device resumes normal operation after PLL lock time (~10 ms). This behavior is defined in Section 7.4.1 and verified in Figure 10 of the DS90CF386MTD/NOPB datasheet.

Can DS90CF386MTD/NOPB be used with non-TI FPD-Link I transmitters?

Yes, DS90CF386MTD/NOPB is compatible with any FPD-Link I-compliant transmitter meeting TIA/EIA-644 LVDS standards, including third-party and custom ASIC transmitters. Its 100 Ω differential input termination, 20–85 MHz clock range, and 7:1 deserialization ratio align with FPD-Link I protocol specifications - enabling interoperability regardless of transmitter manufacturer, provided timing margins (e.g., skew, jitter) fall within DS90CF386MTD/NOPB's 290 ps RxIN skew margin at 85 MHz.