Texas Instruments DS90CF386MTD-TI

Overview

DS90CF386MTD-TI from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC for flat-panel display (FPD) links, converting four 140–595 Mbps LVDS data streams and one 20–85 MHz LVDS clock into parallel 28-bit LVCMOS outputs (24-bit RGB + 4 control bits). It features an internal PLL with no external components, operates at 3.3 V, and supports VGA through SXGA resolutions in embedded display interconnects.

For engineers reviewing the DS90CF386MTD-TI datasheet, DS90CF386MTD-TI pinout, DS90CF386MTD-TI application, or DS90CF386MTD-TI equivalent, this page delivers verified electrical specs, TSSOP-56 and NFBGA-64 package details, timing-critical strobe behavior on RxCLKOUT falling edge, power-down mode (<400 µA), and real-world FPD-Link I interoperability with TI's companion transmitters.

Technical Context

The DS90CF386MTD-TI implements a dedicated PLL-based clock recovery architecture that locks to incoming LVDS clock frequencies from 20 MHz to 85 MHz, enabling precise sampling of serialized 7-bit-per-cycle LVDS data across four differential pairs. Its deserialization logic maps each LVDS input to seven LVCMOS outputs per clock cycle, delivering full 28-bit parallel output aligned to the falling edge of RxCLKOUT.

It supports two distinct LVDS termination schemes: 100-Ω across each differential pair at the receiver input, with separate LVDS_GND, PLL_GND, and LVCMOS VCC domains. The device maintains functional integrity during partial power loss via failsafe bias circuitry and high-impedance LVDS inputs during power-on/off transitions.

Key Specifications

Pinout & Package

DS90CF386MTD-TI is available in two packages: 56-pin TSSOP (DGG, 14.00 mm × 6.10 mm) and 64-pin NFBGA (NZC, 8.00 mm × 8.00 mm, 0.8-mm pitch). Both packages support identical pin functions and thermal metrics (R_θJA = 64.6°C/W for TSSOP, 65.7°C/W for NFBGA).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CF366MTD and SN65LVDS32, DS90CF386MTD uniquely delivers 28-bit FPD-Link I deserialization with integrated PLL, making it irreplaceable for 24-bit RGB + 4-control-bit display interfaces requiring 85 MHz pixel clocks and cable-driven reliability.

Availability

DS90CF386MTD-TI is available at Aetrix Electronics and suitable for embedded LCD display interface, industrial panel PC video link, automotive infotainment head unit, and print engine image data bridge applications requiring stable component supply and long-term lifecycle support.

Supply support for DS90CF386MTD-TI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS90CF386MTD-TI belongs to TI's FPD-Link I family, designed specifically for cost-effective, low-EMI video transport between graphics processors and flat-panel displays in industrial, medical, and automotive systems.

FAQ

What is the maximum data rate supported by DS90CF386MTD-TI?

The DS90CF386MTD-TI supports a maximum per-lane LVDS data rate of 595 Mbps at 85 MHz clock frequency, yielding 2.38 Gbps aggregate throughput across four data lanes. This is confirmed in the datasheet's switching characteristics and typical application diagrams, and enables full 24-bit RGB video transmission at SXGA resolution. DS90CF386MTD-TI achieves this using 7-bit serialization per clock cycle, with precise PLL-based sampling.

Does DS90CF386MTD-TI require external components for PLL operation?

No, DS90CF386MTD-TI integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. The PLL locks automatically to the incoming LVDS clock (20–85 MHz) and generates the internal sampling clock for deserialization. This is explicitly stated in the Features section and validated in the Functional Block Diagram and PLL description in Section 7.3.2 of the DS90CF386MTD-TI datasheet.

How does DS90CF386MTD-TI handle power-down mode?

DS90CF386MTD-TI enters low-power mode when the PWR_DWN pin is driven low (LVCMOS logic level), reducing supply current to ≤400 µA. In this state, all RxOUT outputs are forced low and the PLL stops. The device retains its configuration and resumes normal operation within 1 µs after PWR_DWN is released, as specified in the RPDD timing parameter. DS90CF386MTD-TI also features failsafe biasing during power transitions to prevent latch-up.

Which packages are offered for DS90CF386MTD-TI?

DS90CF386MTD-TI is available in two industry-standard packages: 56-pin TSSOP (DGG, 14.00 mm × 6.10 mm) and 64-pin NFBGA (NZC, 8.00 mm × 8.00 mm, 0.8-mm pitch). The NFBGA offers a 44% smaller PCB footprint than the TSSOP variant, as documented in the Device Information table and Mechanical section of the DS90CF386MTD-TI datasheet. Both packages share identical pin functions and electrical specifications.

Can DS90CF386MTD-TI interface directly with standard LVCMOS LCD timing controllers?

Yes, DS90CF386MTD-TI outputs 28-bit LVCMOS signals (24 RGB + 4 control bits) with VOH ≥ 2.7 V and VOL ≤ 0.3 V at 2 mA load, meeting standard 3.3-V LVCMOS voltage thresholds. Its RxCLKOUT pin provides a falling-edge strobe synchronized to the parallel data, matching the timing requirements of common LCD timing controllers such as those used in TFT modules. DS90CF386MTD-TI has been validated in reference designs for 18- and 24-bit RGB displays.