Texas Instruments DS90CF386MTDX/NOPB

Overview

DS90CF386MTDX/NOPB from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC for flat-panel display (FPD) links, converting four 140–595 Mbps LVDS data streams and one 20–85 MHz LVDS clock into parallel 24-bit RGB + 4 control signals (HSYNC/VSYNC/DE/CNTL). It operates at 3.3 V, consumes ≤135 mA at 85 MHz, and supports VGA through SXGA resolutions in embedded display interfaces.

For engineers reviewing the DS90CF386MTDX/NOPB datasheet, DS90CF386MTDX/NOPB pinout, DS90CF386MTDX/NOPB application, or DS90CF386MTDX/NOPB equivalent, key selection criteria include LVDS input termination (100 Ω), falling-edge RxCLKOUT strobe timing, PWR_DWN-controlled power-down mode (<400 μA), and compatibility with FPD-Link I transmitters in high-noise, space-constrained display interconnects.

Technical Context

The DS90CF386MTDX/NOPB implements an internal PLL that locks to the incoming LVDS clock (20–85 MHz) without external components, generating a stable sampling clock for deserializing seven bits per LVDS channel per cycle. Its five differential LVDS inputs comprise four data pairs and one clock pair, each requiring 100-Ω termination at the receiver pins.

Deserialization yields 28 LVCMOS outputs (RxOUT[27:0]) strobed on the falling edge of RxCLKOUT, with setup/hold times of 2 ns and 3.5 ns respectively at 85 MHz. The device supports both grayscale and worst-case toggling patterns, delivering <142 mW typical power at 85 MHz grayscale operation.

Key Specifications

Pinout & Package

DS90CF386MTDX/NOPB is available in a 56-pin TSSOP (DGG) package (14.00 mm × 6.10 mm body) with exposed thermal pad. Pin functions are validated per TI SNLS055J Rev J datasheet, including dedicated LVDS_GND, PLL_GND, and LVDS_VCC/PLL_VCC supply domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CF366MTDX/NOPB, DS90CF386MTDX/NOPB adds 7-bit data width, CNTL signal support, and NFBGA packaging option; versus SN65LVDS32PW, it integrates full FPD-Link I deserialization and eliminates external logic dependency - reducing total solution size and timing complexity.

Availability

DS90CF386MTDX/NOPB is available at Aetrix Electronics and suitable for LCD panel interconnect, embedded graphics interface, and medical imaging display applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for DS90CF386MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and consumer applications.

The DS90CF386MTDX/NOPB belongs to TI's FPD-Link I serializer/deserializer product line, designed specifically to replace wide parallel RGB interfaces in flat-panel displays with noise-immune, high-speed LVDS links.

FAQ

What is the maximum supported pixel clock frequency for DS90CF386MTDX/NOPB?

The DS90CF386MTDX/NOPB supports LVDS input clock frequencies from 20 MHz to 85 MHz. At 85 MHz, each of the four LVDS data lanes operates at 595 Mbps, enabling full 24-bit RGB + 4 control signal transmission for SXGA (1280×1024) and higher resolutions. This maximum rate is specified under recommended operating conditions with CL = 8 pF load.

Does DS90CF386MTDX/NOPB require external components for PLL operation?

No, DS90CF386MTDX/NOPB does not require external components for PLL operation. Its internal PLL locks to the incoming 20–85 MHz LVDS clock without external capacitors or resistors. However, proper bypassing of VCC, LVDS_VCC, and PLL_VCC rails with 0.1-μF ceramic capacitors near each supply pin is mandatory to ensure low-jitter clock recovery.

How is the RxCLKOUT signal timed relative to the deserialized data outputs on DS90CF386MTDX/NOPB?

On DS90CF386MTDX/NOPB, all 28 RxOUT signals are strobed on the falling edge of RxCLKOUT. Timing specifications define 2 ns setup time (RSRC) and 3.5 ns hold time (RHRC) relative to this falling edge at 85 MHz, ensuring reliable capture by downstream LVCMOS logic with adequate timing margin.

Can DS90CF386MTDX/NOPB interface directly with a 3.3-V LVCMOS display controller?

Yes, DS90CF386MTDX/NOPB provides 28 LVCMOS-compatible outputs (RxOUT[27:0]) with VOH ≥2.7 V and VOL ≤0.3 V at 3.3 V supply, meeting standard 3.3-V LVCMOS voltage thresholds. Its outputs drive standard CMOS loads up to 8 pF with 1.8–3.5 ns transition times, making it fully interoperable with commercial 3.3-V display controllers.

What happens to the outputs of DS90CF386MTDX/NOPB when the PWR_DWN pin is asserted?

When PWR_DWN is pulled low, DS90CF386MTDX/NOPB enters power-down mode, reducing supply current to ≤400 μA. During this state, all RxOUT[27:0] outputs are actively driven low, and RxCLKOUT stops toggling. This behavior prevents floating buses and ensures deterministic state during standby or thermal shutdown sequences.