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Texas Instruments DS90CF386SLC/NOPB
- Part No.:
- DS90CF386SLC/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 64-LFBGA
- Datasheet:
-
DS90CF386SLC/NOPB.pdf
- Description:
- IC INTFACE SPECIALIZED 64NFBGA
- Quantity:
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Product details
Overview
DS90CF386SLC/NOPB from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC for flat-panel display (FPD) links, converting four LVDS data streams and one LVDS clock into parallel 24-bit RGB + 4 control signals (HSYNC/VSYNC/DE/CNTL) at up to 85 MHz. It features an internal PLL with no external components, <142 mW typical power at 85 MHz grayscale, and supports VGA/SVGA/XGA/SXGA displays in embedded video interfaces.
For engineers reviewing the DS90CF386SLC/NOPB datasheet, DS90CF386SLC/NOPB pinout, DS90CF386SLC/NOPB application, or DS90CF386SLC/NOPB equivalent, key selection criteria include 28-bit parallel output mapping, 100-Ω LVDS termination requirement, falling-edge strobed RxCLKOUT timing, and compatibility with FPD-Link I transmitters across PCB traces or LVDS cables.
Technical Context
The DS90CF386SLC/NOPB implements a dedicated FPD-Link I receiver architecture with five differential LVDS inputs (four data + one clock), phase-locking to input clock frequencies from 20 MHz to 85 MHz. Its internal PLL recovers the clock and generates a synchronized RxCLKOUT signal used to strobe all 28 LVCMOS outputs on the falling edge.
Each LVDS data channel operates at 140–595 Mbps, delivering up to 2.38 Gbps aggregate throughput. The device requires external 100-Ω differential termination per LVDS pair and supports power-down mode via active-low PWR_DWN pin, reducing supply current to ≤400 μA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Standard | TIA/EIA-644 LVDS compliant; requires 100-Ω differential termination per pair |
| Data Width | 28-bit parallel LVCMOS output: 24-bit RGB + 4 control bits (HSYNC/VSYNC/DE/CNTL) |
| Max Clock Rate | 85 MHz input LVDS clock; enables 595 Mbps per LVDS lane and 2.38 Gbps total throughput |
| Power Consumption | ≤142 mW typical at 85 MHz grayscale; ≤1.44 mW max in power-down mode |
| ESD Rating | ±7 kV HBM; ensures robust handling during board assembly and system integration |
| Operating Temp | –10°C to +70°C free-air temperature; validated for industrial display environments |
| Supply Voltage | 3.0 V to 3.6 V nominal VCC; supports standard 3.3-V system rails with ≤100 mVPP noise |
Pinout & Package
DS90CF386SLC/NOPB is packaged in a 56-pin TSSOP (DGG) with 14.00 mm × 6.10 mm body size and 0.5-mm lead pitch. Thermal resistance is RθJA = 64.6°C/W. Pin functions are validated per TI SNLS055J Rev J datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN0+ / RxIN0− | LVDSDifferential Data Input Pair 0 | Accepts first serialized 7-bit LVDS data stream; requires 100-Ω termination across pins |
| RxIN1+ / RxIN1− | LVDSDifferential Data Input Pair 1 | Accepts second serialized 7-bit LVDS data stream; matched routing critical for skew control |
| RxIN2+ / RxIN2− | LVDSDifferential Data Input Pair 2 | Accepts third serialized 7-bit LVDS data stream; referenced to LVDS_GND and LVDS_VCC |
| RxIN3+ / RxIN3− | LVDSDifferential Data Input Pair 3 | Accepts fourth serialized 7-bit LVDS data stream; enables full 28-bit deserialization |
| RxCLKIN+ / RxCLKIN− | LVDSDifferential Clock Input | Carries recovered 20–85 MHz clock; PLL locks to this signal to generate RxCLKOUT |
| RxCLKOUT | LVCMOS Clock Output | Falling-edge strobe synchronizing all 28 RxOUT signals; matches transmitter timing for latch alignment |
| PWR_DWN | Active-Low Power-Down Control | Drives all RxOUT low when asserted; reduces ICC to ≤400 μA without affecting input bias state |
| RxOUT[0:27] | LVCMOS Parallel Data Outputs | 28 single-ended outputs mapped per Figure 8: RxOUT[0:23] = RGB, RxOUT[24:27] = HSYNC/VSYNC/DE/CNTL |
| VCC / GND / LVDS_VCC / LVDS_GND / PLL_VCC / PLL_GND | Power and Ground Terminals | Dedicated supply domains isolate LVCMOS outputs, LVDS receivers, and PLL for jitter reduction |
Key Features
| Feature | Design Value |
|---|---|
| No-external-component PLL | Eliminates external loop filter components; simplifies layout and reduces BOM count for FPD-Link I systems |
| Falling-edge RxCLKOUT strobe | Enables direct interface with standard LVCMOS latches without polarity inversion logic |
| 100-Ω LVDS termination support | Validated input structure accepts industry-standard termination; avoids signal integrity issues on long traces |
| Low-power down mode | Reduces dynamic current to microamp range while maintaining input bias stability during idle periods |
| ESD-hardened I/O | ±7 kV HBM rating protects against assembly ESD events without requiring external TVS diodes |
Applications
| Embedded LCD Display Interface | Industrial Panel PC Video Link |
|---|---|
|
Use Scenario: Connecting GPU output to 24-bit RGB LCD panel over 150-mm flexible cable in medical imaging console. IC Role / Device Role / Timing Role: Deserializes 4-lane LVDS video stream into parallel RGB + sync signals; provides RxCLKOUT as falling-edge strobe for panel timing controller. Use Value: Replaces 28-wire parallel interface, cutting EMI by >20 dB and enabling thinner flex cable routing within tight chassis space. |
Use Scenario: Transmitting high-resolution video from ARM-based HMI processor to 10.1-inch TFT display in factory automation terminal. IC Role / Device Role / Timing Role: Receives FPD-Link I serial stream from DS90C387 transmitter; outputs synchronized 24-bit RGB with HSYNC/VSYNC for precise frame capture. Use Value: Supports XGA (1024×768) at 60 Hz with <1 ns inter-pair skew margin, meeting industrial display refresh consistency requirements. |
| Open LDI-to-RGB Bridge | Digital Signage Video Transport |
|
Use Scenario: Converting OpenLDI source (e.g., laptop dock) to RGB interface for legacy display module in retail kiosk. IC Role / Device Role / Timing Role: Acts as protocol-transparent physical layer bridge; maps LDI's 4-data-lane format directly to 28-bit LVCMOS RGB+control bus. Use Value: Enables drop-in replacement of aging LDI receivers without FPGA re-design; maintains full 85 MHz bandwidth for SXGA support. |
Use Scenario: Distributing digital video from media player to multiple 1920×1080 displays in airport information system using daisy-chained LVDS cabling. IC Role / Device Role / Timing Role: Receives serialized video over 2-meter shielded LVDS cable; outputs low-skew parallel data to display driver ASIC. Use Value: Achieves <290 ps LVDS input skew margin at 85 MHz, ensuring reliable operation despite cable length variations and connector tolerances. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF366MTD/NOPB | 21-bit output (18-bit RGB + 3 control); 3 LVDS data lanes; lower pin count (48-TSSOP) | Suitable for 18-bit RGB panels (e.g., SVGA, XGA) but lacks CNTL bit and 4th data lane | Select when panel resolution ≤1280×1024 and control signal count ≤3; saves PCB area and cost |
| SN65LVDS32PW | Quad LVDS receiver only (no deserialization or PLL); 4-channel, single-ended CMOS outputs | Requires external deserializer and clock recovery; not a functional substitute for FPD-Link I | Use only for custom LVDS signal conditioning where full FPD-Link I protocol stack is implemented elsewhere |
Compared with DS90CF366MTD/NOPB, DS90CF386SLC/NOPB adds 7-bit data width, CNTL signal support, and higher throughput for 24-bit RGB panels; SN65LVDS32PW lacks integrated PLL and deserialization, making it unsuitable as a direct alternative for FPD-Link I systems.
Availability
DS90CF386SLC/NOPB is available at Aetrix Electronics and suitable for embedded LCD display interfaces, industrial panel PCs, and digital signage video transport requiring stable component supply and long-term manufacturing continuity.
Supply support for DS90CF386SLC/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in display interface solutions.
The DS90CF386SLC/NOPB belongs to TI's FPD-Link I family, designed specifically for high-speed, low-EMI video transmission between graphics processors and flat-panel displays in industrial and commercial equipment.
FAQ
What is the maximum data rate supported by DS90CF386SLC/NOPB?
The DS90CF386SLC/NOPB supports an input LVDS clock up to 85 MHz, resulting in 595 Mbps per LVDS data lane and a total throughput of 2.38 Gbps. This enables full 24-bit RGB video transmission at resolutions including SXGA (1280×1024) at 60 Hz, as confirmed in TI SNLS055J Section 3 and Table 6.6.
Does DS90CF386SLC/NOPB require external components for PLL operation?
No, DS90CF386SLC/NOPB integrates a fully self-contained PLL that requires no external capacitors or resistors. As stated in the Features section and Section 7.3.2 of the datasheet, the PLL locks directly to the incoming LVDS clock, eliminating loop filter components and simplifying board design.
How is the 28-bit output mapped on DS90CF386SLC/NOPB?
The DS90CF386SLC/NOPB maps its 28 LVCMOS outputs as RxOUT[0:23] = 24-bit RGB (R[7:0], G[7:0], B[7:0]) and RxOUT[24:27] = HSYNC, VSYNC, DE, and CNTL, per Figure 8 in the TI SNLS055J datasheet. This mapping is fixed and non-configurable.
What is the function of the PWR_DWN pin on DS90CF386SLC/NOPB?
The PWR_DWN pin on DS90CF386SLC/NOPB is an active-low control that places the device into ultra-low-power mode (<400 μA ICC), driving all RxOUT signals low while preserving input bias stability. It is intended for use during video blanking or system sleep states, as detailed in Section 7.4.1.
Can DS90CF386SLC/NOPB interface directly with a 3.3-V FPGA I/O bank?
Yes, DS90CF386SLC/NOPB outputs standard 3.3-V LVCMOS signals with VOH ≥2.7 V and VOL ≤0.3 V under 2-mA load, matching LVTTL/LVCMOS voltage thresholds. Its 3.0–3.6 V VCC range and ±15-μA input leakage ensure safe, rail-to-rail compatibility with 3.3-V FPGA I/O banks without level-shifting.
DS90CF386SLC/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-LFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 64-NFBGA (8x8)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF386SLC/NOPB FAQ
1.How can I place an order for DS90CF386SLC/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF386SLC/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF386SLC/NOPB reliable?
The price and inventory of DS90CF386SLC/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF386SLC/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CF386SLC/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF386SLC/NOPB transactions.
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4.How is shipping managed for DS90CF386SLC/NOPB?
DS90CF386SLC/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF386SLC/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF386SLC/NOPB?
For technical support, including DS90CF386SLC/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF386SLC/NOPB requirements.
6.How does Aetrix verify that DS90CF386SLC/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF386SLC/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF386SLC/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF386SLC/NOPB?
All DS90CF386SLC/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF386SLC/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF386SLC/NOPB part is unused and in its original packaging.
Return procedure for DS90CF386SLC/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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