Texas Instruments DS90CF386SLCX/NOPB

Overview

DS90CF386SLCX/NOPB from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC used as the receiver in FPD-Link I flat-panel display interfaces. It converts four 140–595 Mbps LVDS data streams and one 20–85 MHz LVDS clock into 28 parallel LVCMOS outputs (24-bit RGB + 4 control signals), operates with <142 mW typical power at 85 MHz, supports VGA/SXGA displays, and features an internal PLL requiring no external components.

For engineers reviewing the DS90CF386SLCX/NOPB datasheet, DS90CF386SLCX/NOPB pinout, DS90CF386SLCX/NOPB application, or DS90CF386SLCX/NOPB equivalent, key selection criteria include LVDS input count (4 data + 1 clock), 28-bit parallel output mapping, TSSOP-56 package compatibility, power-down mode behavior, and FPD-Link I timing compliance up to 85 MHz.

Technical Context

The DS90CF386SLCX/NOPB implements a dedicated FPD-Link I receiver architecture with five differential LVDS inputs (four data lanes + one clock lane), an internal PLL that locks to incoming LVDS clock frequencies from 20 MHz to 85 MHz, and a serial-to-parallel converter that recovers 7 bits per lane per clock cycle for a total of 28 LVCMOS outputs.

Its functional block includes LVDS receivers with 100-Ω differential termination support, a jitter-sensitive PLL optimized for low-noise VCC bypassing, and LVCMOS drivers strobing on the falling edge of RxCLKOUT. The device supports both grayscale and worst-case toggling patterns, with defined skew margins (290 ps at 85 MHz) and setup/hold times referenced to RxCLKOUT.

Key Specifications

Pinout & Package

The DS90CF386SLCX/NOPB is packaged in a 56-pin TSSOP (DGG) with 14.00 mm × 6.10 mm body size and 0.5-mm lead pitch. Pin functions are electrically validated per TI SNLS055J Rev J.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CF366MTDX/NOPB, DS90CF386SLCX/NOPB adds 7-bit data capacity and CNTL signal support for 24-bit RGB panels; compared with SN65LVDS32PW, it integrates full deserialization and clock recovery - eliminating external logic and reducing BOM count by ≥3 components.

Availability

DS90CF386SLCX/NOPB is available at Aetrix Electronics and suitable for embedded LCD timing interfaces, industrial panel PC video links, and open LDI-to-RGB bridge designs requiring stable component supply and long-term display subsystem continuity.

Supply support for DS90CF386SLCX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with broad industrial and automotive design-in support.

The DS90CF386SLCX/NOPB belongs to TI's FPD-Link I serializer/deserializer product line, engineered specifically for cost-sensitive, high-reliability flat-panel display interconnects in commercial and industrial equipment.

FAQ

What is the maximum data rate supported by DS90CF386SLCX/NOPB?

The DS90CF386SLCX/NOPB supports an LVDS clock input up to 85 MHz, resulting in a per-lane bit rate of 595 Mbps and an aggregate throughput of 2.38 Gbps across four data lanes. This enables full 24-bit RGB + 4 control signal transmission for resolutions up to SXGA (1280×1024) at 60 Hz. The DS90CF386SLCX/NOPB datasheet specifies timing margins and skew tolerance validated at this maximum rate.

Does DS90CF386SLCX/NOPB require external components for PLL operation?

No, the DS90CF386SLCX/NOPB contains a fully integrated PLL that locks to the incoming LVDS clock without requiring external capacitors, resistors, or crystal references. The PLL is designed to operate across the full 20–85 MHz input range and generates the RxCLKOUT signal internally. External 100-Ω differential termination resistors are required on each LVDS input pair, but no PLL-specific components are needed.

How does the power-down mode function on DS90CF386SLCX/NOPB?

Asserting the PWR_DWN pin low places the DS90CF386SLCX/NOPB into power-down mode, reducing supply current to <400 μA while driving all RxOUT pins low. The device retains its configuration and exits power-down synchronously upon PWR_DWN deassertion, with PLL lock reacquired within 10 ms. This mode is intended for display blanking or system sleep states where active video is suspended but fast resume is required.

What package options are available for DS90CF386SLCX/NOPB?

The DS90CF386SLCX/NOPB is offered in a 56-pin TSSOP (DGG) package with 14.00 mm × 6.10 mm body size and 0.5-mm lead pitch. While the DS90CF386 family also includes an NFBGA variant (NZC, 64-pin), the DS90CF386SLCX/NOPB suffix specifically denotes the TSSOP-56 version. No SOIC, QFP, or other package variants exist for this orderable part number.

Can DS90CF386SLCX/NOPB interface directly with standard LVCMOS display controllers?

Yes, the DS90CF386SLCX/NOPB provides 28 LVCMOS-compatible outputs (RxOUT[0:27]) with VOH ≥ 2.7 V and VOL ≤ 0.3 V at 3.3 V supply, meeting standard 3.3-V LVCMOS voltage thresholds. Its RxCLKOUT falling edge serves as the synchronous strobe for all outputs, aligning with common display controller sampling requirements. No level-shifting or timing translation is needed when interfacing with FPGA-, ASIC-, or MCU-based RGB display interfaces.