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Texas Instruments DS90CF388AVJD/NOPB
- Part No.:
- DS90CF388AVJD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 100-TQFP
- Datasheet:
-
DS90CF388AVJD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:180
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Product details
Overview
DS90CF388AVJD/NOPB from Texas Instruments (formerly National Semiconductor) is a dual-pixel LVDS display receiver IC for FPD-Link interfaces, converting 8-channel LVDS differential data and clock into 48-bit TTL RGB + 3 control outputs (HSYNC/VSYNC/DE). It supports up to 112 MHz pixel clock, delivers 5.7 Gbps aggregate bandwidth, and operates from 3.0–3.6 V supply in industrial temperature range (−10°C to +70°C) for QXGA-resolution flat-panel displays.
For engineers reviewing the DS90CF388AVJD/NOPB datasheet, DS90CF388AVJD/NOPB pinout, DS90CF388AVJD/NOPB application, or DS90CF388AVJD/NOPB equivalent, key selection considerations include dual-pixel timing recovery, programmable DE strobe edge, pre-emphasis compatibility with DS90C387A transmitter, RSKM skew margin at 112 MHz, and TQFP-100 package layout constraints.
Technical Context
The DS90CF388AVJD/NOPB implements a PLL-based LVDS clock recovery architecture synchronized to incoming differential clock (RxCLK INP/M), supporting both single- and dual-pixel modes via external configuration. Its internal data sampling window (RSPOS) and 170 ps receiver skew margin (RSKM) at 112 MHz enable robust timing alignment across long cable runs.
It features programmable control strobe polarity (R_FDE), power-down mode (PD) forcing outputs low, STOPCLK indicator for clock loss detection, and compatibility with ANSI/TIA/EIA-644-1995 LVDS standard. The receiver accepts 8 LVDS data pairs (AnP/AnM) and one LVDS clock pair, outputting 51 TTL signals including 16R/16G/16B and HSYNC/VSYNC/DE.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Pixel Clock | 112 MHz - enables QXGA (2048×1536) at 60 Hz with dual-pixel mapping |
| Total Bandwidth | 5.7 Gbps - achieved via 8 × 784 Mbps LVDS lanes, sufficient for 48-bit RGB + 3 control |
| Supply Voltage | 3.0–3.6 V - compatible with standard 3.3 V logic rails; 100 mVp-p noise tolerance |
| Operating Temp | −10°C to +70°C - qualified for industrial display applications, not automotive or extended temp |
| Receiver Skew Margin | 170 ps at 112 MHz - defines minimum allowable interconnect skew + source jitter budget |
| Power-Down Current | 255–300 µA - enables low-power standby without full system shutdown |
| LVDS Input Range | 0–2.4 V differential - compliant with ANSI/TIA/EIA-644-1995; rejects common-mode noise |
Pinout & Package
DS90CF388AVJD/NOPB uses a 100-pin TQFP (VJD100A) package with exposed thermal pad, RoHS-compliant NiPdAu lead finish, and MSL Level-3 moisture sensitivity rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AnP[0:7] | LVDS positive data input | Differential inputs for 8 serialized data channels; mapped to RGB/control bits per FPD-Link protocol |
| AnM[0:7] | LVDS negative data input | Complementary inputs completing 8 differential pairs; require matched PCB trace lengths |
| RxCLK INP / RxCLK INM | LVDS clock input pair | Differential reference clock recovered by internal PLL; determines pixel rate and sampling phase |
| Rn[0:15], Gn[0:15], Bn[0:15] | TTL RGB data outputs | 48-bit parallel CMOS/TTL outputs; drive standard LCD timing controller inputs directly |
| DE, HSYNC, VSYNC | TTL control outputs | 3 active-high sync signals; DE maps to LVDS channel A2; HSYNC/VSYNC use dedicated pins |
| RxCLK OUT | TTL clock output | Falling-edge strobe synchronized to recovered clock; used as data latch signal by downstream logic |
| R_FDE | Control strobe select input | Configures DE active polarity: high = DE high enables data, low = DE low enables data |
| PD | Power-down enable input | Active-low control; forces all outputs low and disables PLL when asserted |
| STOPCLK | LVDS clock presence indicator | Open-drain output; logic high indicates missing RxCLK IN, enabling fault detection in host system |
| VCC / GND / PLLVCC / PLLGND / LVDSVCC / LVDSGND | Power and ground terminals | Separate supplies isolate digital, PLL, and LVDS receiver domains to minimize noise coupling |
Key Features
| Feature | Design Value |
|---|---|
| Programmable DE strobe polarity | R_FDE pin selects whether data is valid on DE high or DE low, enabling direct interface with diverse GPU controllers |
| 170 ps receiver skew margin at 112 MHz | Guarantees reliable data capture across PCB/cable skew up to 170 ps, critical for >2 m cable runs |
| STOPCLK clock-loss indicator | Provides hardware-level fault signaling without software polling, simplifying system diagnostics |
| Backward-compatible FPD-Link receiver | Interoperates with legacy DS90C387A transmitter and supports dual-clock configurations for panel flexibility |
| Low-jitter PLL recovery | Delivers <100 ps cycle-to-cycle jitter on RxCLK OUT at 112 MHz, preserving timing integrity for high-res panels |
Applications
| Medical Imaging Displays | Industrial HMI Panels |
|---|---|
Use Scenario: High-resolution diagnostic monitors requiring QXGA resolution and flicker-free operation in operating rooms. IC Role / Device Role / Timing Role: LVDS receiver recovering pixel clock and RGB data from remote graphics controller over shielded twisted-pair cable. Use Value: 170 ps RSKM ensures timing margin against EMI-induced skew in electrically noisy OR environments. | Use Scenario: Factory-floor HMIs with 10+ meter cable runs between controller and sunlight-readable TFT display. IC Role / Device Role / Timing Role: Dual-pixel LVDS-to-TTL bridge enabling 24-bit color depth at 85 MHz while maintaining DC balance. Use Value: Pre-emphasis compatibility with DS90C387A allows 5 m cable drive at 80 MHz using 1.2 V PRE voltage. |
| Avionics Display Systems | Test & Measurement Equipment |
Use Scenario: Ruggedized cockpit displays needing EMI resilience and deterministic timing for safety-critical overlays. IC Role / Device Role / Timing Role: FPD-Link receiver providing isolated, low-noise RGB interface between video processor and display module. Use Value: Separate PLLVCC/LVDSVCC rails suppress supply noise coupling into recovered clock path. | Use Scenario: Automated optical inspection systems requiring precise pixel-aligned triggering of image capture. IC Role / Device Role / Timing Role: Timing-critical receiver generating RxCLK OUT falling edge as synchronous strobe for CCD/CMOS sensor readout. Use Value: 2.4 ns setup time (RSRC) at 112 MHz enables sub-nanosecond trigger alignment with pixel data. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS display receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF386AMT/NOPB | Single-pixel 24-bit receiver; no dual-pixel support; max 85 MHz clock; 64-pin TSSOP | Suitable only for SXGA or lower resolutions; lacks RSKM spec and STOPCLK indicator | Select when cost-sensitive designs require only 24-bit color and shorter cable runs (<1.5 m) |
| SN65LVDS32PW | Generic LVDS receiver; no embedded PLL; no RGB mapping; 16-pin TSSOP | Requires external clock generation and parallelization logic; not a drop-in replacement | Choose only for custom LVDS deserialization where full FPD-Link protocol handling is unnecessary |
Compared with DS90CF388AVJD/NOPB, DS90CF386AMT/NOPB reduces pin count and cost but sacrifices QXGA readiness and skew margin; SN65LVDS32PW offers minimal integration and demands significant external logic, making it unsuitable for direct display interface replacement.
Availability
DS90CF388AVJD/NOPB is available at Aetrix Electronics and suitable for medical imaging displays, industrial HMI panels, avionics display systems, and test & measurement equipment requiring stable component supply and long-term lifecycle support.
Supply support for DS90CF388AVJD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired National Semiconductor in 2011 and maintains its high-performance analog and interface product lines, including FPD-Link display interface ICs.
The DS90CF388AVJD/NOPB belongs to TI's Flat Panel Display Link (FPD-Link) receiver family, designed specifically for high-bandwidth, low-EMI transmission of RGB video data between graphics controllers and TFT-LCD panels.
FAQ
What is the maximum supported pixel clock frequency for DS90CF388AVJD/NOPB?
The DS90CF388AVJD/NOPB supports a maximum pixel clock frequency of 112 MHz, enabling QXGA (2048×1536) resolution at 60 Hz in dual-pixel mode. This is confirmed in the Electrical Characteristics table under RCOP (RxCLK OUT Period) and verified by worst-case timing analysis at 112 MHz in the Receiver Switching Characteristics section.
Does DS90CF388AVJD/NOPB support single-pixel mode operation?
Yes, DS90CF388AVJD/NOPB supports single-pixel mode when paired with a DS90C387A transmitter configured with DUAL = GND. In this mode, the receiver processes 24-bit RGB + 3 control signals mapped to the first four LVDS data channels, reducing bandwidth requirements while maintaining full timing compatibility.
What is the function of the STOPCLK pin on DS90CF388AVJD/NOPB?
The STOPCLK pin on DS90CF388AVJD/NOPB is an open-drain output that asserts logic high when the LVDS clock input (RxCLK INP/M) is absent or invalid. It provides hardware-level clock-loss detection without requiring software polling, enabling rapid system fault response in mission-critical displays.
How does DS90CF388AVJD/NOPB handle differential input jitter?
DS90CF388AVJD/NOPB incorporates a PLL-based clock recovery circuit with jitter attenuation capability. At 112 MHz, its cycle-to-cycle jitter on RxCLK OUT is specified ≤100 ps, ensuring stable sampling of recovered data even when input clock jitter reaches ±3 ns, as validated in Figures 13–14 and AN-1059.
What package type and thermal characteristics does DS90CF388AVJD/NOPB use?
DS90CF388AVJD/NOPB uses a 100-pin TQFP (VJD100A) package with exposed thermal pad. Its maximum power dissipation is 2.8 W at +25°C, derating at 18.2 mW/°C above ambient. The package carries MSL Level-3 rating (260°C peak reflow, 168-hour floor life), requiring moisture-sensitive handling per JEDEC J-STD-020.
DS90CF388AVJD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 100-TQFP
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 100-TQFP (14x14)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF388AVJD/NOPB FAQ
1.How can I place an order for DS90CF388AVJD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF388AVJD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF388AVJD/NOPB reliable?
The price and inventory of DS90CF388AVJD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF388AVJD/NOPB is usually 5 days.
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DS90CF388AVJD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF388AVJD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF388AVJD/NOPB?
For technical support, including DS90CF388AVJD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF388AVJD/NOPB requirements.
6.How does Aetrix verify that DS90CF388AVJD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF388AVJD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF388AVJD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF388AVJD/NOPB?
All DS90CF388AVJD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF388AVJD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF388AVJD/NOPB part is unused and in its original packaging.
Return procedure for DS90CF388AVJD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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