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Texas Instruments DS90CF388AVJDX/NOPB
- Part No.:
- DS90CF388AVJDX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 100-TQFP
- Datasheet:
-
DS90CF388AVJDX/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 100TQFP
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
DS90CF388AVJDX/NOPB from Texas Instruments (formerly National Semiconductor) is a dual-pixel LVDS display interface receiver IC designed for high-resolution flat-panel displays up to QXGA. It converts 8 LVDS differential data streams and 1 LVDS clock into 48-bit RGB TTL outputs (16R/16G/16B) plus 3 control signals (DE, HSYNC, VSYNC), operating at pixel clock rates up to 112 MHz with 5.7 Gbps aggregate throughput. It supports backward compatibility with legacy FPD-Link receivers via dual-clock input capability and integrates programmable PLL, pre-emphasis-aware signal recovery, and power-down mode.
For engineers reviewing the DS90CF388AVJDX/NOPB datasheet, DS90CF388AVJDX/NOPB pinout, DS90CF388AVJDX/NOPB application, or DS90CF388AVJDX/NOPB equivalent, this page delivers verified technical context on LVDS-to-TTL conversion timing, skew margin (RSKM ≥170 ps at 112 MHz), dual/single pixel configuration, and real-world cable drive support up to 5 meters with pre-emphasis - all critical for embedded display interface design in industrial HMIs and medical panels.
Technical Context
The DS90CF388AVJDX/NOPB implements a fully integrated LVDS receiver with adaptive PLL-based clock recovery, supporting dual-pixel (48-bit) and single-pixel (24-bit) modes via external DUAL pin configuration on its companion transmitter (DS90C387A). Its internal strobe window (RSPOS) and 170 ps minimum skew margin at 112 MHz enable robust sampling across interconnects with up to ±1 bit-time pair-to-pair deskew.
It features programmable DE strobe edge selection (R_FDE), auto-ranging PLL (PLLSEL tied to VCC), and dedicated STOPCLK output indicating LVDS clock presence. Power-down mode forces TTL outputs low while maintaining <300 µA supply current, and it complies with ANSI/TIA/EIA-644-1995 LVDS standards with differential input thresholds of ±100 mV.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Pixel Clock Rate | 112 MHz - enables QXGA (2048×1536) resolution at 60 Hz with dual-pixel RGB |
| LVDS Input Channels | 8 differential pairs (AnP/AnM ×8) + 1 differential clock pair - matches DS90C387A transmitter output structure |
| TTL Output Format | 48-bit RGB (16R/16G/16B) + DE/HSYNC/VSYNC - direct interface to timing controllers without glue logic |
| Receiver Skew Margin (RSKM) | ≥170 ps at 112 MHz - quantifies usable data sampling window after accounting for cable skew and source jitter |
| Supply Voltage Range | 3.0 V to 3.6 V - compatible with standard 3.3 V systems; LVDS inputs tolerate −0.3 V to +3.6 V |
| Power-Down Current | 255–300 µA - enables low-power standby in portable or energy-sensitive display systems |
| Differential Input Threshold | ±100 mV - ensures reliable LVDS signal detection under noise and common-mode variation |
Pinout & Package
DS90CF388AVJDX/NOPB is housed in a 100-pin TQFP (VJD100A) package with exposed thermal pad, RoHS-compliant NIPDAU finish, and JEDEC Level-3 moisture sensitivity rating (260°C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AnP / AnM (×8) | LVDS differential data inputs | Accept serialized 8-channel LVDS data from DS90C387A; mapped to R/G/B/DE bits per FPD-Link protocol |
| RxCLK INP / RxCLK INM | LVDS differential clock input | Recover pixel clock from LVDS stream; drives internal PLL and output strobe timing |
| Rn, Gn, Bn, DE, HSYNC, VSYNC | TTL-level parallel outputs | 48-bit RGB + 3 control signals; outputs active-low during power-down (PD = low) |
| RxCLK OUT | TTL clock output | Falling-edge strobe synchronized to recovered clock; used as data latch signal by downstream timing controller |
| R_FDE | Control strobe select input | Configures DE polarity: high = DE active-high; low = DE active-low - matches host controller signaling |
| PD | Power-down enable input | Active-low control; asserts low-current state and forces TTL outputs low when deasserted |
| STOPCLK | LVDS clock presence indicator | Logic high when no valid LVDS clock detected; allows system-level fault detection and fallback behavior |
| VCC / GND / LVDSVCC / LVDSGND / PLLVCC / PLLGND | Power and ground terminals | Dedicated supplies isolate digital, LVDS, and PLL domains to minimize noise coupling and ensure jitter performance |
Key Features
| Feature | Design Value |
|---|---|
| Dual-pixel architecture support | Enables native 48-bit RGB interface to QXGA panels; also configurable for single-pixel (24-bit) operation via companion transmitter DUAL pin |
| Programmable DE strobe polarity | R_FDE pin selects active-high or active-low DE assertion - eliminates need for external inverters when interfacing diverse GPU or MCU controllers |
| Receiver skew margin (RSKM) | ≥170 ps at 112 MHz - provides measurable timing safety margin against cable skew, ISI, and source jitter in long-reach LVDS links |
| Auto-ranging PLL with fast lock | Locks within 10 ms across 32.5–112 MHz range; PLLSEL tied to VCC enables seamless frequency adaptation without firmware intervention |
| LVDS clock presence detection | STOPCLK output signals loss of valid LVDS clock - enables fail-safe display blanking or system reset without external monitoring circuitry |
| Low-power shutdown mode | Reduces supply current to ≤300 µA while holding outputs in defined state - critical for battery-backed or always-on display subsystems |
Applications
| Industrial HMI Panels | Medical Imaging Displays |
|---|---|
Use Scenario: High-resolution touchscreen interface in factory automation panel with 10+ meter LVDS cable run between controller and TFT module. IC Role / Device Role / Timing Role: DS90CF388AVJDX/NOPB recovers pixel clock and deserializes dual-pixel LVDS data into parallel TTL RGB for local timing controller, compensating for inter-pair skew and cable attenuation. Use Value: Pre-emphasis-compatible receiver design enables stable 112 MHz operation over 5 m shielded twisted-pair cable without signal integrity degradation or eye closure. |
Use Scenario: DICOM-compliant diagnostic monitor requiring precise color fidelity and zero-frame-drop video streaming from imaging engine. IC Role / Device Role / Timing Role: DS90CF388AVJDX/NOPB acts as deterministic LVDS-to-TTL bridge with sub-200 ps skew margin, ensuring accurate pixel timing alignment across full QXGA frame buffer. Use Value: Guaranteed RSKM ≥170 ps at 112 MHz ensures >3.5 ns setup/hold margin at receiver inputs - eliminating metastability risk in safety-critical image rendering paths. |
| Avionics Display Systems | Test & Measurement Equipment |
Use Scenario: Ruggedized cockpit display using extended-temperature FPD-Link interface between graphics processor and LCD backlight driver board. IC Role / Device Role / Timing Role: DS90CF388AVJDX/NOPB provides EMI-robust LVDS reception with STOPCLK fault signaling and power-down control for hot-swap-capable display modules. Use Value: STOPCLK output enables immediate display blanking upon LVDS link failure - meeting DO-160 lightning-induced transient response requirements. |
Use Scenario: High-speed waveform generator with embedded LCD preview screen requiring glitch-free pixel updates during analog signal generation. IC Role / Device Role / Timing Role: DS90CF388AVJDX/NOPB synchronizes recovered pixel clock to internal DAC timing, enabling precise pixel-aligned trigger events and frame-accurate overlays. Use Value: Programmable R_FDE and falling-edge RxCLK OUT allow direct integration with FPGA-based timing controllers without additional level-shifting or edge alignment logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS display receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF386AMTDX/NOPB | Single-pixel (24-bit) LVDS receiver; no dual-pixel support; lower max clock (85 MHz); 64-pin TSSOP package | Suitable only for SXGA or lower resolutions; lacks RSKM specification and STOPCLK output | Select when cost, board space, or resolution requirements are constrained to ≤SXGA and dual-pixel operation is unnecessary |
| SN65LVDS32PW | Generic LVDS receiver (4-channel); no PLL, no clock recovery, no TTL RGB output - requires external clock and deserialization logic | Not a drop-in replacement; needs FPGA or ASIC to reconstruct pixel data and timing | Choose only for custom LVDS physical layer extension where full display interface functionality is implemented elsewhere |
Compared with DS90CF388AVJDX/NOPB, DS90CF386AMTDX/NOPB offers lower cost and smaller footprint but sacrifices QXGA support and skew margin assurance, while SN65LVDS32PW provides raw LVDS reception only - requiring significant external logic to replicate the integrated display interface function of DS90CF388AVJDX/NOPB.
Availability
DS90CF388AVJDX/NOPB is available at Aetrix Electronics and suitable for industrial HMIs, medical imaging displays, avionics interfaces, and test equipment requiring stable component supply with guaranteed long-term availability and traceable sourcing.
Supply support for DS90CF388AVJDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired National Semiconductor in 2011 and maintains full product support, documentation, and manufacturing continuity for the DS90CF388A family.
This device belongs to TI's legacy FPD-Link display interface portfolio, engineered specifically for high-bandwidth, low-EMI transmission between graphics processors and flat-panel displays in demanding industrial and medical environments.
FAQ
What is the maximum supported resolution for DS90CF388AVJDX/NOPB?
DS90CF388AVJDX/NOPB supports up to QXGA (2048×1536) resolution at 60 Hz using dual-pixel mode at 112 MHz pixel clock. This is achieved by receiving 48-bit RGB data (16R/16G/16B) plus DE/HSYNC/VSYNC over 8 LVDS data lanes and 1 LVDS clock lane. Single-pixel mode supports up to SXGA (1280×1024) at the same clock rate.
Does DS90CF388AVJDX/NOPB require an external clock source?
No, DS90CF388AVJDX/NOPB does not require an external clock source. It performs full clock recovery from the incoming LVDS clock pair (RxCLK INP/RxCLK INM) using an integrated PLL. The recovered clock appears as TTL-level RxCLK OUT with falling-edge strobe timing, eliminating need for separate clock distribution.
How does DS90CF388AVJDX/NOPB handle cable skew in long-reach LVDS links?
DS90CF388AVJDX/NOPB addresses cable skew through its Receiver Skew Margin (RSKM) specification: ≥170 ps at 112 MHz. This margin accounts for inter-pair skew, source jitter (TJCC <100 ps), and ISI, ensuring reliable data sampling even with 5-meter shielded twisted-pair cables. System-level deskew must be handled externally if skew exceeds RSKM.
What is the function of the STOPCLK pin on DS90CF388AVJDX/NOPB?
The STOPCLK pin on DS90CF388AVJDX/NOPB is an open-drain output that goes high when no valid LVDS clock is detected on RxCLK INP/RxCLK INM. It remains low during normal operation. This enables system-level fault detection - for example, triggering display blanking or controller reset upon LVDS link loss - without requiring external monitoring circuitry.
Can DS90CF388AVJDX/NOPB interface directly with a microcontroller GPIO bank?
Yes, DS90CF388AVJDX/NOPB outputs standard 3.3 V TTL-level signals (Rn/Gn/Bn/DE/HSYNC/VSYNC/RxCLK OUT) compatible with most 3.3 V microcontrollers. Its outputs drive ≥2 mA at VOL ≤0.3 V and VOH ≥2.7 V, meeting standard TTL voltage thresholds. No level-shifting is required when interfacing with 3.3 V GPIO banks supporting 24 mA sink/source per pin.
DS90CF388AVJDX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 100-TQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 100-TQFP (14x14)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF388AVJDX/NOPB FAQ
1.How can I place an order for DS90CF388AVJDX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF388AVJDX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF388AVJDX/NOPB reliable?
The price and inventory of DS90CF388AVJDX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF388AVJDX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CF388AVJDX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF388AVJDX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CF388AVJDX/NOPB?
DS90CF388AVJDX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF388AVJDX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF388AVJDX/NOPB?
For technical support, including DS90CF388AVJDX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF388AVJDX/NOPB requirements.
6.How does Aetrix verify that DS90CF388AVJDX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF388AVJDX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF388AVJDX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF388AVJDX/NOPB?
All DS90CF388AVJDX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF388AVJDX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF388AVJDX/NOPB part is unused and in its original packaging.
Return procedure for DS90CF388AVJDX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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