Texas Instruments DS90CF388VJD/NOPB

Overview

DS90CF388VJD/NOPB from Texas Instruments is a dual-pixel LVDS display interface receiver IC designed for high-resolution flat-panel displays up to QXGA (2048×1536). It converts eight LVDS data streams and one LVDS clock into 48-bit parallel CMOS/TTL RGB output with embedded control signals (HSYNC, VSYNC, DE), supporting 40–112 MHz pixel clock rates and delivering up to 5.38 Gbps total bandwidth in dual-pixel mode. It operates from a 3.3 V supply and features DC-balanced deserialization, cable deskew, and programmable strobe edge selection.

For engineers reviewing the DS90CF388VJD/NOPB datasheet, DS90CF388VJD/NOPB pinout, DS90CF388VJD/NOPB application, or DS90CF388VJD/NOPB equivalent, key selection considerations include its 112 MHz dual-pixel clock support, ±1 LVDS bit-time deskew capability (up to 80 MHz), DC-balance auto-detection, 5 V-tolerant TTL outputs, and compatibility with OpenLDI-compliant transmitter pairs such as DS90C387.

Technical Context

The DS90CF388VJD/NOPB implements a PLL-based LVDS-to-TTL deserializer with automatic DC-balance detection: when BAL = HIGH, it identifies whether incoming data originates from a DC-balanced (DS90C387) or legacy non-DC-balanced source and applies appropriate bit mapping. Its DESKEW function-enabled only in DC-balance mode-adjusts sampling strobes to compensate for pair-to-pair skew up to ±1 LVDS bit time.

It supports three operational modes via the DUAL pin: dual-pixel (48-bit input → 48-bit output), single-pixel (24-bit input → 48-bit output), and single-in/dual-out conversion. The receiver provides TTL-level outputs with 2.7 V VOH at −0.4 mA, 0.3 V VOL at 2 mA, and sub-2 ns CMOS/TTL transition times, while rejecting cycle-to-cycle jitter ≤100 ps at 112 MHz.

Key Specifications

Pinout & Package

DS90CF388VJD/NOPB is housed in a 100-pin TQFP (Thin Quad Flat Package) with 0.5 mm pitch, thermally enhanced for display interface applications requiring stable operation at up to +70°C ambient.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS display receiver applications.

Compared with DS90CF388VJD/NOPB, DS90CF386VJD/NOPB sacrifices QXGA support and cable robustness for lower BOM cost, while SN65LVDS32PW lacks integrated deserialization entirely-making both alternatives non-substitutable without significant redesign.

Availability

DS90CF388VJD/NOPB is available at Aetrix Electronics and suitable for high-resolution display interfaces in medical imaging systems, industrial HMIs, automotive instrument clusters, and avionics MFDs requiring stable component supply and long-term production continuity.

Supply support for DS90CF388VJD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in display interface solutions.

The DS90CF388VJD/NOPB belongs to TI's OpenLDI-compliant LDI chipset family, engineered specifically for high-bandwidth, low-EMI digital display links between host processors and flat-panel displays in demanding commercial and industrial environments.

FAQ

What is the maximum supported pixel clock frequency for DS90CF388VJD/NOPB in dual-pixel mode?

The DS90CF388VJD/NOPB supports a maximum pixel clock frequency of 112 MHz in dual-pixel mode, enabling QXGA (2048×1536) resolution at 60 Hz refresh rate with full 48-bit color depth. This is confirmed in the Electrical Characteristics table under "Receiver Switching Characteristics" for RCOP (RxCLK OUT Period) and verified in the Functional Description section stating "40 to 112MHz Clock Support for DS90CF388".

Does DS90CF388VJD/NOPB require an external crystal or reference clock?

No, DS90CF388VJD/NOPB does not require an external crystal or reference clock. It recovers timing directly from the incoming LVDS clock pair (RxCLK INP/RxCLK INM) using an internal PLL, as specified in the Receiver Block Diagram and confirmed in the "Receiver Phase Lock Loop Set" timing parameter (RPLLS = 10 ms).

How does DS90CF388VJD/NOPB handle DC balance detection and what is required to enable it?

DS90CF388VJD/NOPB enables automatic DC-balance detection when the BAL pin is driven HIGH. In this mode, it analyzes the incoming LVDS data stream to determine whether it originates from a DC-balanced DS90C387 or a legacy non-DC-balanced source, then applies the correct deserialization mapping per Tables 3 and 4 of the datasheet. No external configuration or firmware is needed.

Can DS90CF388VJD/NOPB drive a display panel directly, or does it require a separate timing controller?

DS90CF388VJD/NOPB outputs parallel TTL-level RGB data and control signals (HSYNC, VSYNC, DE), but it does not generate panel-specific timing such as gate/source driver clocks or power sequencing. It must be paired with a dedicated display timing controller (TCON) that accepts these signals and drives the TFT panel's row/column drivers accordingly.

What is the purpose of the DESKEW pin on DS90CF388VJD/NOPB and under what conditions does it operate?

The DESKEW pin on DS90CF388VJD/NOPB enables cable deskew functionality, which adjusts internal sampling strobes to compensate for pair-to-pair skew in the LVDS interconnect. It operates only when BAL = HIGH (DC-balance mode enabled) and requires ≥4 clock cycles during vertical/horizontal blanking intervals to complete calibration, as documented in the Pin Descriptions and Figure 13 (RSKMD).