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Texas Instruments DS90CF388VJDX/NOPB
- Part No.:
- DS90CF388VJDX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 100-TQFP
- Datasheet:
-
DS90CF388VJDX/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,399
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Product details
Overview
DS90CF388VJDX/NOPB from Texas Instruments is a dual-pixel LVDS display interface receiver IC designed for high-resolution flat-panel display interconnects. It deserializes 8-channel LVDS data (up to 672 Mbps per channel) into 48-bit CMOS/TTL RGB outputs, supports QXGA resolution at 112 MHz pixel clock, and features DC-balanced data recovery, cable deskew (±1 LVDS bit time), and 5V-tolerant control inputs. It operates from a 3.3 V supply and targets host-to-display links in industrial and medical displays.
For engineers reviewing the DS90CF388VJDX/NOPB datasheet, DS90CF388VJDX/NOPB pinout, DS90CF388VJDX/NOPB application, or DS90CF388VJDX/NOPB equivalent, key selection criteria include dual-pixel LVDS deserialization capability, DC-balance auto-detection, deskew support up to 80 MHz, and compatibility with DS90C387 transmitter-based OpenLDI interfaces.
Technical Context
The DS90CF388VJDX/NOPB implements a PLL-based LVDS-to-TTL parallel conversion architecture with automatic DC-balance mode detection. It accepts eight differential LVDS data pairs and one LVDS clock pair, reconstructing timing via internal PLL lock and recovering 48-bit RGB + control signals (HSYNC, VSYNC, DE) during active video or blanking intervals.
Its DESKEW function operates only in DC-balance mode and adjusts sampling strobes to compensate for fixed inter-pair skew up to ±1 LVDS bit time (e.g., ±12.5 ps at 80 MHz). The receiver provides TTL-level outputs with 1.5–2.0 ns transition times and supports programmable DE strobe edge selection and backward-compatible FPD-Link interoperability via optional second LVDS clock input.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LVDS Input Channels | 8 differential data pairs + 1 clock pair - enables full 48-bit dual-pixel RGB transport over low-noise differential lines |
| Max Pixel Clock Support | 112 MHz - supports QXGA (2048×1536) at dual-pixel rate with 5.38 Gbps aggregate bandwidth |
| DC Balance Mode | Auto-detect enabled when BAL = HIGH - reduces ISI distortion and extends usable cable length beyond 5 m |
| Cable Deskew Range | ±1 LVDS bit time (up to 80 MHz clock) - corrects fixed inter-pair skew without requiring external calibration |
| Supply Voltage | 3.0–3.6 V - compatible with standard 3.3 V logic rails and low-power system design |
| Input Tolerance | 5 V tolerant on CMOS/TTL control inputs (R_FDE, PD, BAL, DESKEW, PLLSEL) - simplifies level-shifting in mixed-voltage systems |
| Power Down Current | 255–300 µA - maintains ultra-low standby power while holding outputs low and clock high |
Pinout & Package
DS90CF388VJDX/NOPB is housed in a 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch) package with dedicated power domains: VCC (TTL I/O), LVDSVCC (LVDS receivers), and PLLVCC (PLL circuitry).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AnP[0:7] | LVDS positive data input | Accepts 8 differential LVDS data streams; mapping depends on DUAL mode and DC-balance setting |
| AnM[0:7] | LVDS negative data input | Complementary input to AnP[n]; forms 8 matched differential pairs for noise-immune data recovery |
| RxCLK INP / RxCLK INM | LVDS clock input pair | Provides reference clock for PLL lock; used to detect DC-balance mode and enable deskew |
| Rn/Gn/Bn[0:15], DE, HSYNC, VSYNC | TTL parallel output bus | 48-bit RGB + 3 control signals; outputs driven at 3.3 V with 1.5–2.0 ns transitions |
| BAL | DC-balance mode select | HIGH enables auto-detect of DC-balanced transmission; LOW forces non-DC-balanced (FPD-Link) mode |
| DESKEW | Deskew enable input | Active HIGH only functional in DC-balance mode; initiates intra-blanking-time deskew calibration |
| PD | Power-down control | LOW asserts power-down state: outputs go low (data) or high (clock), current drops to ≤300 µA |
| STOPCLK | LVDS clock loss indicator | Open-drain output pulled HIGH when no valid LVDS clock detected; LOW indicates stable lock |
Key Features
| Feature | Design Value |
|---|---|
| Auto-detect DC-balance mode | Eliminates manual configuration: DS90CF388VJDX/NOPB identifies DS90C387's BAL setting and applies correct bit mapping |
| Cable deskew with ±1-bit tolerance | Compensates for fixed inter-pair skew up to ±12.5 ps at 80 MHz without external delay elements or calibration firmware |
| 5V-tolerant control inputs | Allows direct connection to 5 V microcontrollers or timing controllers without level shifters on R_FDE, PD, BAL, DESKEW |
| Backward-compatible FPD-Link support | Operates with legacy FPD-Link transmitters via CLK2P/M pins and non-DC-balance mode (BAL = LOW) |
| Low-jitter PLL recovery | Phase lock loop achieves <100 ps cycle-to-cycle jitter rejection at 112 MHz, preserving timing margin in high-speed links |
Applications
| Medical Imaging Displays | Industrial Control Panels |
|---|---|
|
Use Scenario: High-resolution diagnostic monitors (e.g., 2K/4K surgical displays) receiving graphics from embedded GPU or FPGA video pipelines. IC Role / Device Role / Timing Role: LVDS deserializer that recovers dual-pixel RGB data and control signals from long cable runs between controller and panel. Use Value: Enables >5 m cable drive with DC balance and deskew, reducing EMI and eliminating need for shielded coaxial assemblies. |
Use Scenario: Ruggedized HMI panels in factory automation, operating under wide temperature and EMI conditions. IC Role / Device Role / Timing Role: Robust interface receiver converting noise-immune LVDS signals into TTL-level RGB and sync for TFT LCD modules. Use Value: 5V-tolerant control inputs simplify integration with legacy PLC I/O; power-down mode supports energy-efficient standby states. |
| Avionics Display Systems | Digital Signage Controllers |
|
Use Scenario: Cockpit multi-function displays requiring certified, low-jitter, radiation-tolerant video interfaces. IC Role / Device Role / Timing Role: Timing-critical LVDS receiver with sub-100 ps jitter rejection and deterministic deskew for safety-critical rendering. Use Value: Meets DO-254 timing integrity requirements via guaranteed RSKMD ≥ ISI + TPPOS variance + TJCC at 85 MHz. |
Use Scenario: Commercial digital signage players driving large-format QXGA panels over extended backplane traces or flex cables. IC Role / Device Role / Timing Role: Dual-pixel deserializer supporting 112 MHz pixel clocks and auto-negotiated DC-balance for signal integrity over 3+ meter interconnects. Use Value: Eliminates eye-diagram closure due to ISI; deskew ensures setup/hold compliance even with 300 ps intra-pair skew. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS display receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CF564MTD/NOPB | Higher-speed 10-bit-per-lane receiver (up to 135 MHz); supports WQXGA; includes integrated spread-spectrum clocking | Targets next-gen panels beyond QXGA; requires updated layout for 128-pin BGA and tighter impedance control | Select when migrating to >2048×1536 resolution or requiring reduced EMI via SSCG |
| SN65LVDS32PW | Single-channel LVDS receiver (4 data + 1 clock); no deserialization, no DC balance, no deskew; 3.3 V only | Limited to low-bandwidth auxiliary links (e.g., touch controller sync), not main display data paths | Use only for point-to-point control signaling where full 48-bit parallel recovery is unnecessary |
Compared with DS90CF388VJDX/NOPB, DS90CF564MTD/NOPB delivers higher resolution support but demands more complex PCB routing and thermal management, while SN65LVDS32PW offers minimal integration for non-video roles-neither matches the balanced combination of QXGA readiness, auto-DC-balance, and cable deskew in the DS90CF388VJDX/NOPB.
Availability
DS90CF388VJDX/NOPB is available at Aetrix Electronics and suitable for medical imaging displays, industrial HMIs, avionics cockpits, and digital signage controllers requiring stable component supply across long production lifecycles.
Supply support for DS90CF388VJDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 50 years of innovation in high-reliability interface solutions.
The DS90CF388VJDX/NOPB belongs to TI's Flat Panel Display (FPD) Link family, engineered specifically for noise-immune, high-bandwidth, long-cable video interconnects between graphics controllers and LCD/OLED panels.
FAQ
What is the maximum supported pixel clock frequency for DS90CF388VJDX/NOPB in dual-pixel mode?
The DS90CF388VJDX/NOPB supports up to 112 MHz pixel clock frequency in dual-pixel mode, enabling QXGA (2048×1536) resolution with 48-bit RGB data. This corresponds to an aggregate data rate of 5.38 Gbps across all 8 LVDS lanes. Operation above 112 MHz is not specified or guaranteed per the SNLS012H datasheet.
Does DS90CF388VJDX/NOPB require external configuration to detect DC-balanced vs. non-DC-balanced transmission?
No. DS90CF388VJDX/NOPB automatically detects DC-balanced transmission when the BAL pin is HIGH and uses the received LVDS clock signal to determine interface mode. This auto-detection eliminates manual register writes or boot-time configuration, ensuring seamless interoperability with DS90C387 transmitters in either mode.
Can DS90CF388VJDX/NOPB operate with a 5 V input voltage on its control pins?
Yes. DS90CF388VJDX/NOPB features 5 V tolerance on R_FDE, PD, BAL, DESKEW, and PLLSEL control inputs. This allows direct interfacing with 5 V microcontrollers or timing controllers without external level shifters, simplifying system design and reducing BOM count.
What is the purpose of the STOPCLK pin on DS90CF388VJDX/NOPB?
The STOPCLK pin on DS90CF388VJDX/NOPB is an open-drain status indicator that outputs HIGH when no valid LVDS clock is present at RxCLK INP/M, and LOW when a stable clock is detected and PLL lock is achieved. It provides hardware-level clock presence monitoring for system fault detection and safe startup sequencing.
How does the DESKEW function work in DS90CF388VJDX/NOPB, and when is it active?
The DESKEW function in DS90CF388VJDX/NOPB adjusts internal sampling strobes to compensate for fixed inter-pair skew up to ±1 LVDS bit time. It is active only when both BAL = HIGH (DC-balance mode) and DESKEW = HIGH, and requires ≥4 clock cycles during vertical/horizontal blanking intervals to complete calibration.
DS90CF388VJDX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 100-TQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 100-TQFP (14x14)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CF388VJDX/NOPB FAQ
1.How can I place an order for DS90CF388VJDX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CF388VJDX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CF388VJDX/NOPB reliable?
The price and inventory of DS90CF388VJDX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CF388VJDX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CF388VJDX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CF388VJDX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CF388VJDX/NOPB?
DS90CF388VJDX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CF388VJDX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CF388VJDX/NOPB?
For technical support, including DS90CF388VJDX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CF388VJDX/NOPB requirements.
6.How does Aetrix verify that DS90CF388VJDX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CF388VJDX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CF388VJDX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CF388VJDX/NOPB?
All DS90CF388VJDX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CF388VJDX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CF388VJDX/NOPB part is unused and in its original packaging.
Return procedure for DS90CF388VJDX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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