Texas Instruments DS90CF564MTDX/NOPB

Overview

DS90CF564MTDX/NOPB from Texas Instruments is an LVDS receiver IC for flat panel display (FPD) links, converting three LVDS data streams and one LVDS clock into 21-bit CMOS/TTL output (18-bit RGB + 3 control signals). It operates at up to 65 MHz transmit clock frequency, delivers 171 Mbytes/s throughput, features falling-edge data strobe synchronization, and supports XGA (1024×768) resolution in single-pixel-per-clock mode.

For engineers reviewing the DS90CF564MTDX/NOPB datasheet, DS90CF564MTDX/NOPB pinout, DS90CF564MTDX/NOPB application, or DS90CF564MTDX/NOPB equivalent, key selection criteria include LVDS-to-TTL conversion capability, 48-pin TSSOP package compatibility, power-down mode (<0.25 mW), differential input skew margin (600 ps), and compliance with TIA/EIA-644 LVDS standard.

Technical Context

The DS90CF564MTDX/NOPB implements a PLL-based clock recovery architecture that locks to the incoming LVDS clock (RxCLK IN±) and regenerates a clean TTL clock (FPSHIFT OUT) synchronized to recovered data. Its internal sampling window accommodates cable-induced skew and source clock jitter, with a guaranteed 600 ps skew margin at 5 V and 25°C.

It reconstructs 21 parallel TTL outputs-six red, six green, six blue, and three timing/control lines (FPLINE/HSYNC, FPFRAME/VSYNC, DRDY/ENA)-from three differential LVDS data pairs and one differential clock pair, maintaining precise inter-channel alignment per FPD Link timing requirements.

Key Specifications

Pinout & Package

DS90CF564MTDX/NOPB uses a 48-pin TSSOP package (DGG0048A), 12.4–12.6 mm × 6.0–6.2 mm footprint, 1.2 mm max height, RoHS-compliant matte tin lead finish, and moisture sensitivity level 2 (260°C peak reflow).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS-to-TTL FPD Link receiver applications.

Compared with DS90CF564MTD/NOPB, DS90CF564MTDX/NOPB offers identical electrical and timing performance in tape-and-reel format optimized for high-volume SMT placement, whereas SN65LVDS32 lacks FPD Link-specific clock recovery, skew compensation, and 21-bit parallel output mapping - making it unsuitable as a drop-in replacement.

Availability

DS90CF564MTDX/NOPB is available at Aetrix Electronics and suitable for industrial HMI displays, medical diagnostic monitors, avionics cabin displays, and XGA LCD panel interfaces requiring stable component supply across extended product lifecycles.

Supply support for DS90CF564MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and digital signal processing technologies, with leadership in interface, power management, and signal chain solutions.

The DS90CF564MTDX/NOPB belongs to TI's FPD Link family, engineered specifically to replace wide parallel TTL interfaces in flat-panel displays with compact, low-EMI LVDS links while preserving pixel-accurate timing integrity.

FAQ

What is the primary function of the DS90CF564MTDX/NOPB in an FPD Link system?

The DS90CF564MTDX/NOPB functions as an LVDS receiver that converts three differential LVDS data streams and one differential LVDS clock into 21-bit parallel CMOS/TTL outputs - specifically six red, six green, six blue, and three control signals (FPLINE, FPFRAME, DRDY). It recovers timing via an integrated PLL and delivers a synchronized falling-edge FPSHIFT OUT strobe, enabling direct connection to LCD controllers without external clock conditioning. This role is fundamental to the DS90CF564MTDX/NOPB's design as an FPD Link receiver.

Does the DS90CF564MTDX/NOPB require external components for PLL operation?

No, the DS90CF564MTDX/NOPB integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. The PLL locks directly to the incoming LVDS clock (RxCLK IN±) and regenerates a stable, low-jitter FPSHIFT OUT clock aligned to recovered data. This eliminates BOM cost and layout area typically needed for loop filters or reference oscillators - a core feature confirmed in the SNLS107E datasheet under "Features" and "Electrical Characteristics." The DS90CF564MTDX/NOPB thus simplifies system design while maintaining timing accuracy.

What is the significance of the 600 ps skew margin specification for the DS90CF564MTDX/NOPB?

The 600 ps skew margin specifies the maximum allowable combined timing uncertainty - including LVDS cable length-induced skew (typically 10–40 ps/ft) and source clock (TxCLK IN) cycle-to-cycle jitter - within which the DS90CF564MTDX/NOPB guarantees correct sampling of all 21 data bits. This margin ensures robust operation across varying cable types and lengths without requiring precise cable matching. It is measured at VCC = 5 V and TA = 25°C per Figure 16 of the SNLS107E datasheet and directly enables reliable deployment of the DS90CF564MTDX/NOPB in real-world display systems.

How does the power-down mode of the DS90CF564MTDX/NOPB operate, and what is its current draw?

When the PWR DOWN pin is driven low, the DS90CF564MTDX/NOPB enters power-down mode, holding all 21 RxOUT pins in their last valid logic states while reducing supply current to ≤10 μA (typical 1 μA). This mode preserves display state during sleep or standby without requiring external latching. The specification is verified in the "Electrical Characteristics" table under ICCRZ (Receiver Supply Current, Power Down), with test conditions confirming operation across the full −10°C to +70°C temperature range. This behavior is intrinsic to the DS90CF564MTDX/NOPB's architecture and supports energy-efficient display power management.

Is the DS90CF564MTDX/NOPB compatible with standard LVDS signaling, and which specification does it meet?

Yes, the DS90CF564MTDX/NOPB is fully compatible with the TIA/EIA-644 LVDS standard. Its LVDS receiver inputs meet the standard's differential voltage thresholds (±100 mV), common-mode range (0–2.4 V), and input impedance requirements. The device accepts LVDS signals with 250–450 mV differential swing and 1.1–1.37 V common-mode voltage, as specified in the "LVDS RECEIVER DC SPECIFICATIONS" section of SNLS107E. This compliance ensures interoperability with any TIA/EIA-644-compliant transmitter - including the companion DS90CF563 - and forms the foundation of the DS90CF564MTDX/NOPB's role in standardized FPD Link implementations.