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Texas Instruments DS90CP02SP/NOPB
- Part No.:
- DS90CP02SP/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 28-UFQFN Exposed Pad
- Datasheet:
-
DS90CP02SP/NOPB.pdf
- Description:
- IC CROSSPOINT SW 1 X 2:2 28WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,903
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Product details
Overview
DS90CP02SP/NOPB from Texas Instruments is a 1.5 Gbps 2×2 LVDS crosspoint switch optimized for high-speed signal routing over lossy FR-4 backplanes and balanced cables. It supports non-blocking configurations including dual repeater, 1:2 splitter, 2:1 mux, and crossover modes, with LVDS/BLVDS/CML/LVPECL-compatible inputs and LVDS outputs, operating from a single 3.3 V supply across −40°C to +85°C.
For engineers reviewing the DS90CP02SP/NOPB datasheet, DS90CP02SP/NOPB pinout, DS90CP02SP/NOPB application, or DS90CP02SP/NOPB equivalent, key selection considerations include differential jitter performance (≤126 psp-p at 1.5 Gbps), flow-through UQFN-28 pinout for layout simplicity, independent channel enable/control, and support for multiple reconfigurable signal paths without blocking.
Technical Context
The DS90CP02SP/NOPB implements a fully differential, non-blocking 2×2 crosspoint architecture with separate LVTTL control of SEL0/SEL1 (configuration) and EN0/EN1 (output enable). Its input stage accepts LVDS, BLVDS, CML, and LVPECL signal levels (0.05–3.55 V common-mode range), while outputs are strictly LVDS-compliant with 250–575 mV differential swing and 1.09–1.475 V offset voltage.
Switching is governed by a truth table defining eight valid operational modes-including dual-channel repeater, single-channel crossover, and 1:2 splitter-with propagation delays under 3.5 ns, channel-to-channel skew ≤315 ps, and output enable/disable times of 5–150 ns. Power management includes per-channel power-down states reducing static current to 1.4–2.5 mA in full tri-state mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 1.5 Gbps per channel - supports high-speed serial links such as Camera Link, FPD-Link, or industrial vision interfaces |
| Supply Voltage | 3.3 V ±0.3 V - single-rail operation compatible with standard LVDS system power domains |
| Differential Output Swing | 250–575 mV - ensures robust LVDS signaling into 100 Ω differential loads with margin for PCB loss |
| Total Jitter (TJ) | 93–126 psp-p at 1.5 Gbps - meets timing budget requirements for multi-gigabit serial data recovery |
| Propagation Delay | 0.5–3.5 ns - enables precise inter-channel timing alignment in parallel data paths |
| Input Common-Mode Range | 0.05–3.55 V - interoperable with LVPECL, CML, and Bus-LVDS sources without level-shifting |
| Operating Temperature | −40°C to +85°C - qualified for industrial and embedded systems with extended thermal environments |
Pinout & Package
The DS90CP02SP/NOPB is housed in a 28-pin UQFN (NJD0028A) package with exposed thermal pad (DAP), requiring ≥4 vias to ground plane for optimal thermal and AC performance. Pin numbering follows TI's top-view convention with flow-through layout minimizing trace crossovers.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0+, IN0− | Differential Input Pair 0 | Accepts LVDS/BLVDS/CML/LVPECL signals; wide common-mode range enables direct interface to diverse drivers |
| IN1+, IN1− | Differential Input Pair 1 | Second independent input path; selectable via SEL0/SEL1 to either output |
| OUT0+, OUT0− | Differential Output Pair 0 | Routed to IN0± or IN1± per configuration; LVDS-compliant output with controlled swing and skew |
| OUT1+, OUT1− | Differential Output Pair 1 | Independent output path supporting simultaneous or split routing; supports 1:2 splitter mode |
| SEL0, SEL1 | Configuration Select Inputs | LVTTL-level digital controls determining crosspoint mapping (e.g., 00 = IN0→OUT0/OUT1 splitter) |
| EN0, EN1 | Output Enable Inputs | Per-output tri-state control enabling dynamic power gating and bus sharing without signal contention |
| VDD (Pins 11,14,16,18,19,22,25) | Power Supply | Seven dedicated 3.3 V pins reduce IR drop and improve PSRR; requires ≥4 × 0.01 µF low-ESR bypass caps |
| GND / DAP | Ground Reference | Multiple GND pins plus exposed thermal pad (DAP) connected directly to PCB ground plane for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Non-blocking 2×2 crosspoint architecture | Enables any input-to-any-output routing (including simultaneous 1:2 splitting or 2:1 multiplexing) without internal contention |
| Flow-through pinout | Minimizes PCB trace length and layer transitions-reducing insertion loss and crosstalk in high-speed layouts |
| Separate input/output enable control | Allows independent power-down of channels (e.g., disable unused output while keeping input active for monitoring) |
| Low output jitter (≤126 psp-p) | Maintains eye opening at 1.5 Gbps, critical for reliable clock/data recovery in serial link receivers |
| Wide input compatibility (LVDS/CML/LVPECL) | Eliminates need for external level shifters when interfacing with mixed-signal or legacy high-speed sources |
Applications
| Industrial Camera Interface | FPGA I/O Expansion |
|---|---|
Use Scenario: Routing high-speed image data from dual CMOS sensors to a single FPGA processing unit over FR-4 backplane traces. IC Role / Device Role / Timing Role: 2:1 multiplexer selecting between two LVDS camera streams, with sub-3.5 ns propagation delay preserving pixel timing integrity. Use Value: Enables flexible sensor selection without redesigning PCB layout-flow-through pinout simplifies trace routing and maintains signal integrity up to 1.5 Gbps. |
Use Scenario: Expanding limited FPGA LVDS I/O to drive multiple display panels or ADC/DAC modules simultaneously. IC Role / Device Role / Timing Role: Dual-channel repeater buffering and distributing clock/data pairs to separate downstream devices with matched skew. Use Value: Provides deterministic 0.5–3.5 ns delay and ≤315 ps channel-to-channel skew-critical for synchronous multi-display timing alignment. |
| Automotive ADAS Video Hub | Test Equipment Signal Switching |
Use Scenario: Aggregating video feeds from surround-view cameras into a central domain controller using lossy automotive harnesses. IC Role / Device Role / Timing Role: Crossover switch re-mapping input pairs to alternate output lanes to compensate for harness asymmetry or connector swaps. Use Value: Wide 0.05–3.55 V input common-mode range accommodates varying cable-induced DC offsets without signal degradation. |
Use Scenario: Automated test systems requiring dynamic reconfiguration of high-speed stimulus/response paths between instruments and DUTs. IC Role / Device Role / Timing Role: Reconfigurable crosspoint enabling on-the-fly switching between multiple 1.5 Gbps test vectors without physical rewiring. Use Value: LVTTL control (SEL0/SEL1/EN0/EN1) allows microcontroller-based real-time path selection with <150 ns switching latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS crosspoint switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX9152ESE+ | 2×2 LVDS crosspoint with 1.2 Gbps max rate; higher 100 mA supply current; SOIC-16 package | Limited to lower data rates and lacks flow-through pinout-requires more board area and additional termination components | Choose MAX9152ESE+ only if SOIC packaging and legacy 1.2 Gbps compliance are mandatory; not suitable for 1.5 Gbps FR-4 backplane routing. |
| SN65LVDS386DGK | Quad 1:2 LVDS splitter (not crosspoint); fixed topology; no input selection logic; 800 Mbps max rate | Cannot perform 2:1 mux or crossover functions-only supports fanout from one input to two outputs | Use SN65LVDS386DGK only for simple broadcast scenarios where input flexibility is unnecessary and data rate ≤800 Mbps. |
Compared with MAX9152ESE+ and SN65LVDS386DGK, the DS90CP02SP/NOPB uniquely delivers 1.5 Gbps non-blocking 2×2 routing in a space-saving UQFN-28 package with flow-through layout and wide-level input compatibility-making it the only option supporting dynamic reconfiguration at full gigabit speeds in compact industrial or automotive designs.
Availability
DS90CP02SP/NOPB is available at Aetrix Electronics and suitable for industrial camera interfaces, FPGA I/O expansion, automotive ADAS video hubs, and automated test equipment requiring stable component supply and guaranteed long-term availability.
Supply support for DS90CP02SP/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in high-speed interface ICs and signal integrity technologies.
The DS90CP02SP/NOPB belongs to TI's high-speed LVDS interface product line, designed specifically for robust signal routing in noise-sensitive, high-bandwidth applications such as machine vision, automotive video, and test instrumentation.
FAQ
What is the maximum supported data rate for DS90CP02SP/NOPB?
The DS90CP02SP/NOPB is characterized and specified for operation up to 1.5 Gbps per channel, with electrical parameters including jitter, propagation delay, and output swing validated at this rate. Performance remains functional beyond 1.5 Gbps in some configurations but is not guaranteed per datasheet specifications.
Does DS90CP02SP/NOPB support LVPECL input signals?
Yes, DS90CP02SP/NOPB supports LVPECL input signals across its full 0.05–3.55 V common-mode voltage range. The input stage is explicitly rated for LVDS, BLVDS, CML, and LVPECL compatibility-no external level shifting is required when interfacing with LVPECL sources.
What package type and thermal considerations apply to DS90CP02SP/NOPB?
DS90CP02SP/NOPB uses the 28-pin UQFN (NJD0028A) package with an exposed thermal pad (DAP). For optimal thermal performance, the DAP must be connected to the PCB ground plane using at least four thermal vias, and the device exhibits θJA = 29°C/W under standard JEDEC conditions.
Can DS90CP02SP/NOPB operate in a 1:2 splitter configuration?
Yes, DS90CP02SP/NOPB supports 1:2 splitter mode-for example, with SEL0=0 and SEL1=0, both OUT0 and OUT1 route the same IN0 signal while IN1 is powered down. This mode draws ~40 mA supply current and maintains matched output skew for synchronized fanout.
What is the output enable timing behavior of DS90CP02SP/NOPB?
DS90CP02SP/NOPB provides fast output control: tON (enable time) is 50–150 ns, and tOFF (disable time) is 5–12 ns. This allows rapid tri-state transitions for dynamic bus sharing or power gating, with minimal glitch risk due to controlled LVDS output slew rates.
DS90CP02SP/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-UFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Crosspoint Switch
- Circuit:
- 1 x 2:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-UQFN (5x5)
DS90CP02SP/NOPB FAQ
1.How can I place an order for DS90CP02SP/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CP02SP/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CP02SP/NOPB reliable?
The price and inventory of DS90CP02SP/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CP02SP/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CP02SP/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CP02SP/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CP02SP/NOPB?
DS90CP02SP/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CP02SP/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CP02SP/NOPB?
For technical support, including DS90CP02SP/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CP02SP/NOPB requirements.
6.How does Aetrix verify that DS90CP02SP/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CP02SP/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CP02SP/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CP02SP/NOPB?
All DS90CP02SP/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CP02SP/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CP02SP/NOPB part is unused and in its original packaging.
Return procedure for DS90CP02SP/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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