Texas Instruments DS90CP02SPX/NOPB
- Part No.:
- DS90CP02SPX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 28-UFQFN Exposed Pad
- Datasheet:
-
DS90CP02SPX/NOPB.pdf
- Description:
- IC CROSSPOINT SW 1 X 2:2 28WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS90CP02SPX/NOPB from Texas Instruments is a 1.5 Gbps 2×2 LVDS crosspoint switch optimized for high-speed signal routing over lossy FR-4 backplanes and balanced cables. It supports non-blocking configurations including dual repeater, 1:2 splitter, 2:1 mux, and crossover modes, with LVDS/BLVDS/CML/LVPECL-compatible inputs and LVDS outputs, operating from a single 3.3 V supply across −40°C to +85°C.
For engineers reviewing the DS90CP02SPX/NOPB datasheet, DS90CP02SPX/NOPB pinout, DS90CP02SPX/NOPB application, or DS90CP02SPX/NOPB equivalent, this page delivers verified electrical parameters, flow-through UQFN-28 pin mapping, configuration truth table behavior, jitter performance at 1.5 Gbps, and real-world use cases in serial link redundancy and differential bus switching.
Technical Context
The DS90CP02SPX/NOPB implements fully differential signal paths with independent control of two input pairs (IN0±, IN1±) and two output pairs (OUT0±, OUT1±), enabling any-to-any connection via SEL0/SEL1 logic. Its non-blocking architecture supports simultaneous routing without internal contention, and separate EN0/EN1 enables per-channel power-down to reduce static current to 2.5 mA.
Input common-mode range spans 0.05 V to 3.55 V, accepting LVDS, BLVDS, CML, and LVPECL signals; outputs are strictly LVDS-compliant with 250–575 mV differential swing into 100 Ω. Propagation delay is 0.5–3.5 ns, channel-to-channel skew ≤315 ps in splitter mode, and total jitter ≤126 psp-p at 1.5 Gbps under PRBS23-1 pattern.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 1.5 Gbps per channel - supports PCIe Gen1, SATA I, and LVDS camera links without retiming. |
| Supply Voltage | 3.0–3.6 V - single 3.3 V rail simplifies power design; bypassing requires ≥4 × 0.01 µF low-ESR capacitors. |
| Differential Output Swing | 250–575 mV into 100 Ω - meets ANSI/TIA/EIA-644-A LVDS standard for noise margin and interconnect compatibility. |
| Total Jitter (TJ) | 93–126 psp-p at 1.5 Gbps - measured with PRBS23-1 pattern; enables <10−12 BER in backplane applications. |
| Operating Temperature | −40°C to +85°C - qualified for industrial embedded systems and telecom line cards without derating. |
| Static Supply Current | 42–60 mA (dual active), 22–30 mA (single active) - low-power operation reduces thermal load in dense PCB layouts. |
| Input Common-Mode Range | 0.05 V to 3.55 V - interoperates with CML (1.0 V), LVPECL (1.3 V), and LVDS (1.2 V) sources without level-shifting. |
Pinout & Package
DS90CP02SPX/NOPB uses a 28-pin UQFN package (package code NJD0028A) with exposed thermal pad (DAP) soldered to ground plane. The flow-through pinout minimizes trace length and crosstalk: inputs occupy left side (pins 9–13), controls center-left (pins 5–7), power distributed across top/bottom (VDD on pins 11,14,16,18,19,22,25; GND on pins 1–4,17,21,DAP), outputs right side (pins 23–27).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0+, IN0− | Differential Input Pair 0 | Accepts LVDS/BLVDS/CML/LVPECL signals; common-mode range 0.05–3.55 V enables direct interface to multiple driver families. |
| IN1+, IN1− | Differential Input Pair 1 | Independent second input path; allows redundant source selection or dual-data-stream routing without shared front-end. |
| OUT0+, OUT0− | Differential Output Pair 0 | LVDS-compliant outputs configurable to route either IN0± or IN1±; supports point-to-point or 1:2 fanout. |
| OUT1+, OUT1− | Differential Output Pair 1 | Second independent LVDS output; enables simultaneous delivery of distinct data streams or mirrored signals. |
| SEL0, SEL1 | Configuration Select Inputs | LVTTL-level control bits defining switch mode (repeater, mux, splitter, crossover); truth table defines 8 valid states. |
| EN0, EN1 | Output Enable Inputs | Per-output enable/disable; drives outputs to high-impedance state with tOFF ≤12 ns for dynamic power management. |
| VDD (pins 11,14,16,18,19,22,25) | Power Supply | Single 3.3 V rail; multiple pins reduce IR drop and improve PSRR; requires local 0.01 µF bypassing at each pin. |
| GND / DAP | Ground Reference | Primary ground path via exposed DAP (thermal pad); must connect to PCB ground plane with ≥4 vias for optimal EMI and thermal performance. |
Key Features
| Feature | Design Value |
|---|---|
| Non-blocking 2×2 crosspoint architecture | Enables any input-to-output mapping (e.g., IN0→OUT0 + IN1→OUT1, or IN0→OUT0 + IN0→OUT1) without internal contention or timing penalty. |
| Flow-through UQFN-28 pinout | Minimizes PCB trace length and layer transitions; eliminates need for vias between adjacent differential pairs, preserving signal integrity at 1.5 Gbps. |
| Multi-standard input compatibility | Accepts LVDS, BLVDS, CML, and LVPECL signals within one device-eliminates external level shifters in mixed-signal backplanes. |
| Per-channel power-down control | EN0/EN1 independently disable outputs, reducing ICC to 1.4–2.5 mA; critical for hot-swap and low-power standby in telecom modules. |
| Low output jitter (≤126 psp-p) | Ensures timing margin in high-speed serial links; meets jitter budget requirements for 1.5 Gbps SATA and Camera Link interfaces. |
Applications
| High-Speed Backplane Routing | Redundant Serial Link Switching |
|---|---|
Use Scenario: Routing LVDS video or control data across multi-slot FR-4 backplanes in industrial automation chassis where trace loss exceeds 15 dB at 750 MHz. IC Role / Device Role / Timing Role: Crosspoint switch providing loss compensation via signal regeneration and flexible path selection between slot controllers and I/O modules. Use Value: Maintains signal integrity at 1.5 Gbps without retimers; non-blocking architecture allows dynamic reconfiguration during system boot or failover. |
Use Scenario: Providing automatic failover between primary and backup camera links in machine vision inspection systems. IC Role / Device Role / Timing Role: Dual-channel repeater/mux that routes active stream to both outputs while monitoring link health via control logic. Use Value: Enables seamless switchover with <150 ns configuration time (tSW) and no packet loss; LVDS outputs ensure EMI compliance in factory environments. |
| Dual-Stream Video Distribution | LVDS Bus Multiplexing |
Use Scenario: Distributing synchronized dual-camera feeds from a single sensor array to separate image processors in automotive ADAS domain controllers. IC Role / Device Role / Timing Role: 1:2 splitter replicating one input stream to two independent LVDS outputs with matched propagation delay (tSKCC ≤315 ps). Use Value: Eliminates skew-induced frame misalignment; identical output characteristics ensure pixel-perfect synchronization across processing paths. |
Use Scenario: Sharing a single LVDS test probe interface among multiple FPGA-based subsystems on a shared carrier board. IC Role / Device Role / Timing Role: 2:1 mux selecting between two LVDS sources under LVTTL control, with fast enable/disable (tON/tOFF ≤150/12 ns). Use Value: Reduces test fixture complexity; flow-through pinout allows direct routing without stubs, preserving signal fidelity up to 1.5 Gbps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS crosspoint switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX9152ESE+ | 1.25 Gbps max rate; 20-pin SOIC package; higher ICC (85 mA typical); no CML/LVPECL input support. | Best suited for cost-sensitive, lower-speed industrial control where board space is less constrained. | Select MAX9152ESE+ only if data rate ≤1.25 Gbps and mixed-input compatibility is not required. |
| SN65LVDS386DGGR | 2×2 LVDS repeater only (no mux/crossover); fixed routing; 1.6 Gbps; 16-pin VQFN; no SEL/EN control logic. | Applicable when static dual-channel repeat is sufficient and dynamic reconfiguration is unnecessary. | Choose SN65LVDS386DGGR for simplified, low-jitter repeater applications without switching flexibility. |
Compared with DS90CP02SPX/NOPB, MAX9152ESE+ trades speed and input flexibility for legacy package availability, while SN65LVDS386DGGR offers higher bandwidth but lacks programmable routing-making DS90CP02SPX/NOPB the only option supporting full 2×2 crosspoint functionality with multi-standard inputs and per-channel power control.
Availability
DS90CP02SPX/NOPB is available at Aetrix Electronics and suitable for high-speed backplane routing, redundant serial link switching, dual-stream video distribution, and LVDS bus multiplexing requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for DS90CP02SPX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in signal integrity and industrial-grade reliability.
The DS90CP02SPX/NOPB belongs to TI's high-speed LVDS interface portfolio, designed specifically for robust, low-jitter signal routing in lossy PCB environments such as telecom backplanes, industrial automation chassis, and machine vision systems.
FAQ
What is the maximum supported data rate for DS90CP02SPX/NOPB?
The DS90CP02SPX/NOPB is characterized and specified for reliable operation up to 1.5 Gbps per channel. This rating is validated across the full industrial temperature range (−40°C to +85°C) and with 100 Ω differential termination. Performance metrics-including jitter (≤126 psp-p), propagation delay (0.5–3.5 ns), and rise/fall times (50–215 ps)-are all guaranteed at this rate per the SNLS267A datasheet.
Does DS90CP02SPX/NOPB support LVPECL or CML input levels?
Yes, DS90CP02SPX/NOPB explicitly supports LVPECL and CML input levels in addition to LVDS and BLVDS. Its wide input common-mode range (0.05 V to 3.55 V) accommodates typical LVPECL (≈1.3 V) and CML (≈1.0 V) common-mode voltages without external biasing or level shifting, as confirmed in Table 1 and the "Features" section of the SNLS267A datasheet.
What package type and thermal pad configuration does DS90CP02SPX/NOPB use?
DS90CP02SPX/NOPB uses a 28-pin UQFN package (TI package code NJD0028A) with an exposed thermal pad (DAP) that must be soldered to the PCB ground plane. The DAP serves as the primary ground connection and requires ≥4 thermal vias for optimal AC performance and thermal dissipation, as detailed in the "Power" section of the pin description table and mechanical drawing SPA28A.
How does the configuration control logic work on DS90CP02SPX/NOPB?
DS90CP02SPX/NOPB uses two LVTTL-level select inputs (SEL0, SEL1) and two enable inputs (EN0, EN1) to define eight valid operating modes-including dual repeater, 1:2 splitter, 2:1 mux, and crossover-per the Configuration Select Truth Table in the SNLS267A datasheet. Invalid states (e.g., SEL0=0/SEL1=0/EN0=1/EN1=0) are explicitly documented and must be avoided in system firmware.
What is the power consumption of DS90CP02SPX/NOPB in dual active mode?
In dual active mode (both inputs and outputs enabled), DS90CP02SPX/NOPB draws 42–60 mA from the 3.3 V supply, corresponding to 139–198 mW total power. This value is measured with 100 Ω differential loads and includes all internal circuitry; power drops to 22–30 mA when one channel is powered down via ENx, and to 1.4–2.5 mA in full shutdown (EN0=EN1=1).
DS90CP02SPX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-UFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Crosspoint Switch
- Circuit:
- 1 x 2:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-UQFN (5x5)
DS90CP02SPX/NOPB FAQ
1.How can I place an order for DS90CP02SPX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CP02SPX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CP02SPX/NOPB reliable?
The price and inventory of DS90CP02SPX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CP02SPX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CP02SPX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CP02SPX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CP02SPX/NOPB?
DS90CP02SPX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CP02SPX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CP02SPX/NOPB?
For technical support, including DS90CP02SPX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CP02SPX/NOPB requirements.
6.How does Aetrix verify that DS90CP02SPX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CP02SPX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CP02SPX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CP02SPX/NOPB?
All DS90CP02SPX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CP02SPX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CP02SPX/NOPB part is unused and in its original packaging.
Return procedure for DS90CP02SPX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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