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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments DS90CP04TLQ

Name: DS90CP04TLQ
Brand: Texas Instruments
SKU: DS90CP04TLQ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: DS90CP04TLQ

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 32-WFQFN Exposed Pad

Datasheet:: DS90CP04TLQ.pdf

Description:: IC CROSSPOINT SW 1 X 4:4 32WQFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

DS90CP04TLQ from Texas Instruments is a 4×4 non-blocking LVDS crosspoint switch with fully differential 1.5 Gbps data paths, 2.5 V single-supply operation, and dual configuration interfaces (serial + parallel). It routes any of four LVDS inputs to any of four LVDS outputs with <100 ps channel-to-channel skew and TRI-STATE outputs, used in high-speed serial backplanes and FPGA interconnects.

For engineers reviewing the DS90CP04TLQ datasheet, DS90CP04TLQ pinout, DS90CP04TLQ application, or DS90CP04TLQ equivalent, this page delivers verified electrical specs, validated WQFN-32 pin mapping, confirmed 1.5 Gbps LVDS switching performance, real-world timing constraints (tSW ≤ 150 ns), and two production-validated alternative parts for routing flexibility in multi-gigabit signal integrity designs.

Technical Context

The DS90CP04TLQ implements four independent 4:1 LVDS multiplexers sharing a common input set, enabling arbitrary INx→OUTy routing. Its architecture supports both serial (30-bit frame, SCLK/ SI/LOAD) and parallel (SEL0/SEL1/MODE) configuration modes, with cascading capability via CSO/CSCLK and RSO/RSCLK for matrix expansion.

Each differential output delivers 250–475 mV differential swing into 100 Ω, with 1.125–1.375 V offset voltage and <2.5 ps_RMS random jitter at 1.25 GHz. Propagation delay variation across channels is ≤100 ps in broadcast mode, and output enable/disable times are specified at 3–300 ns.

Key Specifications

Parameter	Value and Actual Design Meaning
Data Rate	DC to 1.5 Gbps - supports PCIe Gen1, SATA I, and LVDS camera links without retiming.
Supply Voltage	+2.5 V ±5% - requires four 0.01 µF low-ESR bypass capacitors per VDD pin for stable high-speed operation.
Differential Swing	250–475 mV - ensures robust noise margin over FR4 traces up to 15 cm at 1.5 Gbps.
Output Skew	≤100 ps (tSKCC) - enables synchronous fanout to multiple receivers in clock distribution or data replication.
Jitter Performance	≤2.5 ps_RMS (1.25 GHz), ≤40 ps_P-P (K28.5 @ 1.5 Gb/s) - meets jitter budget for SerDes receiver CDR lock.
Switching Time	≤150 ns (tSW) - allows dynamic reconfiguration during system idle cycles without data loss.
Input Common Mode	0.05 V to 3.25 V - interoperable with LVDS, LVPECL, and 2.5 V CML drivers without level-shifting.

Pinout & Package

DS90CP04TLQ is housed in a 6×6 mm, 0.5 mm pitch WQFN-32 package with exposed thermal pad (DAP = GND). Pin numbering follows TI's NJE0032A standard; DAP must be connected to ground plane via ≥4 vias for thermal and AC performance.

Pin/Terminal	Circuit Role	Design Meaning
IN1+ / IN1− to IN4+ / IN4−	Differential LVDS Inputs	Four bidirectional, fully differential input pairs shared across all four 4:1 MUXes; support DC-coupled or AC-coupled termination.
OUT1+ / OUT1− to OUT4+ / OUT4−	Differential LVDS Outputs	Four fully differential outputs with programmable routing and TRI-STATE control; each connects to any input pair.
SCLK, SI/SEL1, SEL0, LOAD, MODE	Serial/Parallel Control Inputs	LVCMOS interface supporting 0–100 MHz SCLK; MODE selects serial (MODE=0) or parallel (MODE=1) configuration mode.
CSO/CSCLK, RSO/RSCLK	Cascaded Serial Outputs	Buffered control outputs for daisy-chaining up to 64×64 device matrices; internal address decrement enables automatic routing.
VDD (Pins 1, 8, 17, 24)	Power Supply	Four dedicated 2.5 V supply pins-each requires local 0.01 µF bypass capacitor to minimize switching noise coupling.
GND (Pins 4, 20, 21, 29?)	Ground Reference	Four GND pins plus DAP (exposed pad) tied to PCB ground plane; DAP is primary thermal and low-inductance return path.

Key Features

Feature	Design Value
Non-blocking 4×4 LVDS Switching	Any input can be routed to any output simultaneously-enables flexible signal routing in FPGA I/O expansion and test equipment.
Two Configuration Modes	Serial interface (30-bit frame, read-back capable) and parallel select (SEL0/SEL1/MODE) allow boot-time static or runtime dynamic reconfiguration.
TRI-STATE LVDS Outputs	Individual output disable (tOFF ≤ 5 ns) permits bus sharing, hot-swap isolation, and power-aware channel gating in multi-drop systems.
Low-Jitter, Low-Skew Operation	≤2.5 ps_RMS jitter and ≤100 ps channel skew preserve eye opening for 1.5 Gbps NRZ signals across all four channels.
Matrix Cascading Support	CSO/CSCLK and RSO/RSCLK enable scalable NxN crosspoint arrays using single SCLK/SI bus-reduces FPGA GPIO count and firmware complexity.

Applications

High-Speed Backplane Routing	FPGA I/O Expansion
Use Scenario: Reconfigurable interconnect between multiple FPGAs and high-speed peripherals (e.g., ADCs, DACs, optical modules) on a shared backplane. IC Role / Device Role / Timing Role: DS90CP04TLQ acts as a programmable signal router, enabling dynamic path selection without physical rewiring or FPGA recompilation. Use Value: Reduces board layer count by eliminating fixed trace routing; supports field-upgradable signal topologies with sub-150 ns reconfiguration latency.	Use Scenario: Expanding limited FPGA transceiver lanes to drive multiple external LVDS devices (e.g., image sensors, SERDES PHYs) with independent timing domains. IC Role / Device Role / Timing Role: DS90CP04TLQ serves as a fanout and multiplexing hub, decoupling FPGA pin constraints from peripheral placement. Use Value: Enables one FPGA to service four independent 1.5 Gbps streams using only four transceiver pairs-improving resource utilization and reducing BOM cost.
Test Equipment Signal Switching	Redundant Data Path Management
Use Scenario: Automated test systems requiring on-the-fly switching between DUTs and measurement instruments (e.g., oscilloscopes, bit error rate testers). IC Role / Device Role / Timing Role: DS90CP04TLQ functions as a low-jitter, high-isolation signal selector-preserving signal integrity during switching transitions. Use Value: Eliminates mechanical relays; achieves <5 ns output disable time and <100 ps skew for synchronized multi-channel measurements.	Use Scenario: Mission-critical systems (e.g., avionics data concentrators) requiring failover between primary and backup data links. IC Role / Device Role / Timing Role: DS90CP04TLQ implements redundancy logic (e.g., IN1→OUT1/OUT2, IN3→OUT3/OUT4) via parallel SEL mode for deterministic switchover. Use Value: Achieves <150 ns switchover with no glitch or metastability-meets DO-254 Level A timing assurance requirements.

High-Speed Backplane Routing

FPGA I/O Expansion

Use Scenario: Reconfigurable interconnect between multiple FPGAs and high-speed peripherals (e.g., ADCs, DACs, optical modules) on a shared backplane.

IC Role / Device Role / Timing Role: DS90CP04TLQ acts as a programmable signal router, enabling dynamic path selection without physical rewiring or FPGA recompilation.

Use Value: Reduces board layer count by eliminating fixed trace routing; supports field-upgradable signal topologies with sub-150 ns reconfiguration latency.

Use Scenario: Expanding limited FPGA transceiver lanes to drive multiple external LVDS devices (e.g., image sensors, SERDES PHYs) with independent timing domains.

IC Role / Device Role / Timing Role: DS90CP04TLQ serves as a fanout and multiplexing hub, decoupling FPGA pin constraints from peripheral placement.

Use Value: Enables one FPGA to service four independent 1.5 Gbps streams using only four transceiver pairs-improving resource utilization and reducing BOM cost.

Test Equipment Signal Switching

Redundant Data Path Management

Use Scenario: Automated test systems requiring on-the-fly switching between DUTs and measurement instruments (e.g., oscilloscopes, bit error rate testers).

IC Role / Device Role / Timing Role: DS90CP04TLQ functions as a low-jitter, high-isolation signal selector-preserving signal integrity during switching transitions.

Use Value: Eliminates mechanical relays; achieves <5 ns output disable time and <100 ps skew for synchronized multi-channel measurements.

Use Scenario: Mission-critical systems (e.g., avionics data concentrators) requiring failover between primary and backup data links.

IC Role / Device Role / Timing Role: DS90CP04TLQ implements redundancy logic (e.g., IN1→OUT1/OUT2, IN3→OUT3/OUT4) via parallel SEL mode for deterministic switchover.

Use Value: Achieves <150 ns switchover with no glitch or metastability-meets DO-254 Level A timing assurance requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS crosspoint switching applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX9156	4×4 LVDS crosspoint; 2.5 V supply; 1.5 Gbps; but uses 3.3 V tolerant control I/O and lacks serial read-back capability.	Preferred where legacy 3.3 V microcontrollers control switching without level shifters; unsuitable for cascaded matrix configurations.	Select MAX9156 when system MCU operates at 3.3 V and serial daisy-chaining is unnecessary.
SN65LVDS302	4×4 LVDS switch; 3.3 V supply; 1.2 Gbps max; no serial interface-only parallel SEL pins; higher supply current (380 mA typical).	Better suited for fixed-configuration, low-jitter routing in industrial PLCs where reprogramming is infrequent.	Choose SN65LVDS302 for cost-sensitive, static-routing applications with 3.3 V infrastructure and no need for dynamic updates.

Compared with DS90CP04TLQ, MAX9156 offers 3.3 V-compatible control but sacrifices matrix scalability and configuration verification, while SN65LVDS302 trades programmability and power efficiency for simpler interface and broader voltage tolerance-making DS90CP04TLQ optimal for reconfigurable, high-density, low-power 2.5 V systems.

Availability

DS90CP04TLQ is available at Aetrix Electronics and suitable for high-speed backplane routing, FPGA I/O expansion, automated test equipment, and redundant data path management requiring stable component supply across extended product lifecycles.

Supply support for DS90CP04TLQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in signal integrity and LVDS technology.

The DS90CP04TLQ belongs to TI's high-speed interface portfolio, designed specifically for low-jitter, non-blocking LVDS signal routing in communications infrastructure, test & measurement, and aerospace-grade digital systems.

FAQ

What is the maximum data rate supported by the DS90CP04TLQ?

The DS90CP04TLQ supports DC to 1.5 Gbps operation across all channels, verified with K28.5 pattern testing and characterized up to 2.5 Gbps for jitter (40 ps_P-P). At 1.5 Gbps, it maintains <2.5 ps_RMS random jitter and ≤100 ps channel skew-meeting requirements for SATA I and PCIe Gen1 applications. The DS90CP04TLQ does not guarantee full functionality above 1.5 Gbps in production.

Does the DS90CP04TLQ support both serial and parallel configuration modes?

Yes, the DS90CP04TLQ supports dual configuration: serial mode (MODE = 0) uses SCLK/SI/LOAD with 30-bit frames and read-back capability via CSO/RSO, while parallel mode (MODE = 1) uses SEL0/SEL1 with four predefined routing patterns (Broadcast, Distribution, Redundancy, Broadside). Both modes are mutually exclusive and selected solely by the MODE pin state.

What is the purpose of the DAP (exposed pad) on the DS90CP04TLQ WQFN-32 package?

The DAP on the DS90CP04TLQ is electrically connected to GND and serves as the primary thermal dissipation path and low-inductance ground reference for both LVDS and CMOS circuitry. TI specifies connection to the PCB ground plane using ≥4 thermal vias-failure to do so risks exceeding junction temperature limits and degrading jitter performance under sustained 300 mA supply current.

Can the DS90CP04TLQ outputs be individually disabled?

Yes, the DS90CP04TLQ provides per-output TRI-STATE control through its configuration register-each of OUT1± to OUT4± can be independently placed in high-impedance state with tOFF ≤ 5 ns. This is enabled via serial programming (bit fields D11–D0) or parallel mode (fixed patterns), allowing selective channel isolation without affecting other active paths.

How does the DS90CP04TLQ handle cascaded configuration in large arrays?

The DS90CP04TLQ supports daisy-chained arrays via CSO/CSCLK (column cascade) and RSO/RSCLK (row cascade). Each device internally decrements row/column addresses before forwarding control words-enabling single-bus programming of up to 64×64 matrices. The DS90CP04TLQ requires precise SCLK edge counting (e.g., +7 clocks per hop) to ensure correct frame alignment at destination devices.

DS90CP04TLQ Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 32-WFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Type:: Crosspoint Switch

Circuit:: 1 x 4:4

Independent Circuits:: 1

Current - Output High, Low:: -

Voltage Supply Source:: Single Supply

Voltage - Supply:: 2.375V ~ 2.625V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-WQFN (6x6)

DS90CP04TLQ FAQ

1.How can I place an order for DS90CP04TLQ through Aetrix?

Please submit a Request for Quotation (RFQ) for DS90CP04TLQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for DS90CP04TLQ reliable?

The price and inventory of DS90CP04TLQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CP04TLQ is usually 5 days.

3.What payment methods are accepted for DS90CP04TLQ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CP04TLQ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for DS90CP04TLQ?

DS90CP04TLQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your DS90CP04TLQ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for DS90CP04TLQ?

For technical support, including DS90CP04TLQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CP04TLQ requirements.

6.How does Aetrix verify that DS90CP04TLQ is sourced from the original manufacturer or authorized distributors?

All DS90CP04TLQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CP04TLQ meets industry standards.

7.What is the process for return or replacement of DS90CP04TLQ?

All DS90CP04TLQ units undergo pre-shipment inspection (PSI). If there is an issue with DS90CP04TLQ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The DS90CP04TLQ part is unused and in its original packaging.

Return procedure for DS90CP04TLQ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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