My Inquiry
My Account
Texas Instruments DS90CP22MT/NOPB
- Part No.:
- DS90CP22MT/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS90CP22MT/NOPB.pdf
- Description:
- IC CROSSPOINT SW 1 X 2:2 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:184
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90CP22MT/NOPB from Texas Instruments is a 2×2 LVDS crosspoint switch IC designed for high-speed serial interconnect routing in backplane, rack-mounted, and fault-tolerant systems. It supports DC–800 Mbps operation with 65 ps (typ) peak-to-peak jitter, 35 ps (typ) output channel-to-channel skew, and operates from a single +3.3 V supply. Its non-blocking architecture enables dynamic reconfiguration between 1:2 splitter, 2:1 mux, repeater, or crosspoint modes - critical for signal distribution and redundancy switching in telecom and industrial data links.
For engineers reviewing the DS90CP22MT/NOPB datasheet, DS90CP22MT/NOPB pinout, DS90CP22MT/NOPB application, or DS90CP22MT/NOPB equivalent, key selection criteria include its LVDS/LVPECL-compatible inputs, TRI-STATE enable control per output, sub-1.3 ns propagation delay, and TSSOP-16 package compatibility with high-density PCB layouts requiring low-skew differential signaling at 800 Mbps.
Technical Context
The DS90CP22MT/NOPB implements a fully differential LVDS signal path from input to output, eliminating pulse width distortion and enabling robust noise immunity in noisy environments. Its internal logic decodes two SEL pins to configure four distinct functional modes - including 1:2 splitter (SEL0=SEL1=0), repeater (SEL0=0, SEL1=1), crosspoint switch (SEL0=1, SEL1=0), and mirrored 1:2 splitter (SEL0=SEL1=1).
Each LVDS receiver accepts both LVDS and LVPECL input levels without external level-shifting, while outputs drive 75 Ω or 100 Ω loads with 285–440 mV differential voltage (VOD) and tightly controlled offset voltage (VOS = 1.0–1.45 V). TRI-STATE control via independent EN pins allows dynamic output disable with <4.5 ns disable time and 55 ns enable recovery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 800 Mbps - supports full-rate serial links in backplane fan-out and point-to-point interconnects |
| Peak-to-Peak Jitter | 65 ps (typ) at 800 Mbps with PRBS23−1 pattern - ensures clean eye opening for reliable high-speed sampling |
| Propagation Delay | 1.3 ns (typ) - enables tight timing budgets in multi-stage LVDS signal chains |
| Output Skew | 35 ps (typ) channel-to-channel - maintains phase alignment across dual outputs in splitter/repeater mode |
| Supply Voltage | +3.3 V (3.0–3.6 V range) - compatible with standard LVDS power domains and eliminates need for auxiliary rails |
| Power Dissipation | 330 mW (typ) - enables thermal management in dense TSSOP-16 layouts without forced cooling |
| Operating Temp | −40°C to +85°C - qualified for industrial and telecom infrastructure environments |
Pinout & Package
DS90CP22MT/NOPB is housed in a 16-pin TSSOP (PW) package, 4.4 mm × 5.0 mm footprint, 1.2 mm max height, with exposed pad for thermal enhancement and mechanical stability. Pin 1 index area located at top-left corner; JEDEC MO-153 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0+, IN0− | Differential LVDS Input Channel 0 | Accepts LVDS or attenuated LVPECL signals; no internal fail-safe biasing - requires external termination if unused |
| IN1+, IN1− | Differential LVDS Input Channel 1 | Independent second input path; enables true 2×2 crosspoint routing or primary/backup selection |
| OUT0+, OUT0− | Differential LVDS Output Channel 0 | Configurable per SEL/EN logic; supports 75 Ω or 100 Ω loads with 285–440 mV VOD |
| OUT1+, OUT1− | Differential LVDS Output Channel 1 | Matched to OUT0 for <35 ps skew in splitter mode; independently TRI-STATEable via EN1 |
| EN0, EN1 | Output Enable Control (active-high) | Drives respective output pair into high-impedance state; reduces ICCD from 125 mA to 55 mA when disabled |
| SEL0, SEL1 | Mode Selection Inputs (CMOS/TTL) | Configure functional mode per Table 1: 1:2 splitter, repeater, crosspoint, or mirrored splitter |
| VCC, GND | Power Supply and Reference | Single 3.3 V rail powers all circuitry; internal regulation ensures stable LVDS biasing across temperature |
| NC | No Connect | Two unconnected pins - must remain floating; no internal connection or function |
Key Features
| Feature | Design Value |
|---|---|
| LVDS/LVPECL Input Compatibility | Accepts LVPECL directly (with optional attenuation) - eliminates external level translators in mixed-signal backplanes |
| Configurable Functional Modes | Four SEL-defined modes (splitter, repeater, crosspoint, mirrored split) - enables one device to replace multiple discrete routing functions |
| Independent TRI-STATE Control | Separate EN0/EN1 pins per output pair - allows dynamic output isolation without affecting other channels |
| Low Skew & Low Jitter | 35 ps (typ) channel-to-channel skew and 65 ps (typ) Pk-Pk jitter at 800 Mbps - preserves signal integrity in timing-critical links |
| Robust Input Threshold | ±100 mV receiver threshold - tolerates common-mode noise up to ±1.2 V while maintaining valid logic detection |
Applications
| Backplane Signal Distribution | Fault-Tolerant Redundancy Switching |
|---|---|
|
Use Scenario: Distributing a single high-speed serial link (e.g., camera sensor output or FPGA transceiver) across two downstream processing modules on separate rack cards. IC Role / Device Role / Timing Role: 1:2 LVDS signal splitter with matched output skew and identical amplitude on both paths. Use Value: Eliminates need for two separate LVDS drivers; maintains <35 ps skew between outputs to ensure synchronous capture at receivers. |
Use Scenario: Selecting between primary and backup data paths in avionics or industrial control systems where continuous uptime is mandatory. IC Role / Device Role / Timing Role: 2:1 LVDS multiplexer with <1.2 ns switch time and sub-ns propagation delay matching. Use Value: Enables seamless failover with <2 ns timing disruption - avoids packet loss or frame sync errors during switchover. |
| LVDS Signal Repeating | Rack-Mounted Serial Bus Expansion |
|
Use Scenario: Restoring signal amplitude and edge integrity after long trace runs (>30 cm) on a motherboard or midplane. IC Role / Device Role / Timing Role: Two-channel LVDS repeater with 1.3 ns propagation delay and <65 ps jitter addition. Use Value: Recovers degraded eye diagrams without retiming; extends usable reach of LVDS links beyond standard 25 cm limits. |
Use Scenario: Fanning out a single LVDS clock or data bus to multiple blade servers or I/O modules in a 19-inch rack system. IC Role / Device Role / Timing Role: Crosspoint switch supporting arbitrary input-to-output mapping across hot-swappable slots. Use Value: Enables flexible topology reconfiguration via SEL pins - avoids fixed-wiring constraints in modular hardware designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS crosspoint switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LVDS22DR | Lower max rate (400 Mbps), no LVPECL input support, SOIC-8 package | Limited to shorter-reach, lower-bandwidth links; lacks SEL-configurable modes | Choose when cost sensitivity outweighs speed and flexibility requirements |
| DS90CP22M-8/NOPB | Identical electrical specs and functionality; differs only in SOIC-16 package (6.2 mm × 10.3 mm vs. TSSOP's 4.4 mm × 5.0 mm) | Same use cases but requires larger PCB area and higher thermal mass | Prefer DS90CP22MT/NOPB for space-constrained, high-density layouts needing TSSOP footprint |
Compared with SN65LVDS22DR and DS90CP22M-8/NOPB, DS90CP22MT/NOPB uniquely delivers 800 Mbps operation with LVPECL compatibility and compact TSSOP packaging - making it optimal for next-generation backplane and modular system designs demanding minimal skew, fast switching, and layout efficiency.
Availability
DS90CP22MT/NOPB is available at Aetrix Electronics and suitable for backplane signal distribution, fault-tolerant redundancy switching, and LVDS repeater applications requiring stable component supply, consistent parametric performance, and long-term industrial lifecycle support.
Supply support for DS90CP22MT/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in LVDS and differential signaling technologies.
The DS90CP22 product line was engineered specifically for high-reliability, high-speed serial interconnect in telecom infrastructure, industrial automation, and test equipment - emphasizing low jitter, configurable routing, and robust noise immunity.
FAQ
What is the maximum supported data rate for DS90CP22MT/NOPB?
The DS90CP22MT/NOPB supports DC to 800 Mbps operation with verified performance under PRBS23−1 pattern testing. At this rate, it delivers 65 ps (typ) peak-to-peak jitter and maintains <35 ps channel-to-channel skew - meeting stringent timing requirements for high-speed serial links in backplane and rack-mounted systems. The DS90CP22MT/NOPB achieves this using fully differential LVDS signal paths and optimized internal routing.
Does DS90CP22MT/NOPB support LVPECL input signals directly?
Yes, DS90CP22MT/NOPB LVDS receiver inputs accept LVPECL signal levels directly, though an external attenuation network may be required depending on driver output swing. The input threshold remains within ±100 mV, and common-mode range spans 0.05 V to 3.25 V - ensuring reliable detection across both LVDS and LVPECL sources without level-shifting circuitry. This capability is explicitly confirmed in the DS90CP22MT/NOPB datasheet's "LVDS RECEIVER DC SPECIFICATIONS" table.
How does the SEL pin configuration affect DS90CP22MT/NOPB functionality?
The two SEL pins (SEL0, SEL1) determine DS90CP22MT/NOPB's operational mode per a defined truth table: SEL0=0/SEL1=0 enables 1:2 splitter mode; SEL0=0/SEL1=1 activates repeater mode; SEL0=1/SEL1=0 configures crosspoint switching; SEL0=1/SEL1=1 selects mirrored 1:2 splitter. Each mode alters internal signal routing without changing pin behavior - allowing dynamic reconfiguration in-system. This logic is implemented in hardwired combinational logic inside the DS90CP22MT/NOPB die.
Can both outputs of DS90CP22MT/NOPB be disabled independently?
Yes, DS90CP22MT/NOPB provides independent TRI-STATE control via EN0 and EN1 pins - each disabling one output pair (OUT0± or OUT1±) without affecting the other. When asserted low, EN0 or EN1 places its associated outputs in high-impedance state and reduces total supply current from 125 mA (typ) to 55 mA (typ). This feature enables selective output isolation in multi-drop or shared-bus architectures, and is validated in the DS90CP22MT/NOPB AC Electrical Characteristics table under TPHZ/TPHZ timing parameters.
What package type is used for DS90CP22MT/NOPB and what are its key mechanical features?
DS90CP22MT/NOPB uses a 16-pin TSSOP (PW) package measuring 4.4 mm × 5.0 mm with 0.65 mm lead pitch and 1.2 mm maximum height. It complies with JEDEC MO-153, includes an exposed thermal pad, and features pin 1 indexing in quadrant Q1 per tape-and-reel standards. The compact footprint supports high-density PCB layouts, and the package's thermal characteristics - including 0.866 W max power dissipation at 25°C - are specified in the DS90CP22MT/NOPB Package Option Addendum.
DS90CP22MT/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Crosspoint Switch
- Circuit:
- 1 x 2:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
DS90CP22MT/NOPB FAQ
1.How can I place an order for DS90CP22MT/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CP22MT/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CP22MT/NOPB reliable?
The price and inventory of DS90CP22MT/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CP22MT/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CP22MT/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CP22MT/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CP22MT/NOPB?
DS90CP22MT/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CP22MT/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CP22MT/NOPB?
For technical support, including DS90CP22MT/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CP22MT/NOPB requirements.
6.How does Aetrix verify that DS90CP22MT/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CP22MT/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CP22MT/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CP22MT/NOPB?
All DS90CP22MT/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CP22MT/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CP22MT/NOPB part is unused and in its original packaging.
Return procedure for DS90CP22MT/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90CP22MT/NOPB Tags
-
SN74HC138DR
Texas Instruments
-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage
-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments
-
74CBTLV3257GUX
Nexperia USA Inc.
-
74HC154BQ,118
Nexperia USA Inc.
-
P3S0200GMX
NXP USA Inc.
-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments
-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments
-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
