Texas Instruments DS90CR215MTD/NOPB
- Part No.:
- DS90CR215MTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CR215MTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS90CR215MTD/NOPB from Texas Instruments is a 21-bit LVDS transmitter IC that converts parallel CMOS/TTL data into three differential LVDS data streams plus one LVDS clock stream, operating at up to 66 MHz with 1.386 Gbps total throughput and 290 mV differential output swing. It implements rising-edge data strobing, supports +3.3 V single-supply operation, and integrates a PLL requiring no external components. It is used in high-speed serial link applications such as flat-panel display interfaces and industrial camera data transmission.
For engineers reviewing the DS90CR215MTD/NOPB datasheet, DS90CR215MTD/NOPB pinout, DS90CR215MTD/NOPB application, or DS90CR215MTD/NOPB equivalent, key selection considerations include its 48-pin TSSOP package, 21-bit parallel-to-serial conversion capability, LVDS compliance per TIA/EIA-644, −40°C to +85°C operating range, and power-down mode consuming <0.5 mW.
Technical Context
The DS90CR215MTD/NOPB employs a phase-locked loop (PLL) to generate and synchronize the LVDS transmit clock with input data, enabling deterministic timing alignment across all 21 bits. Its internal architecture multiplexes 21 TTL/CMOS inputs into three 7-bit LVDS data lanes plus one dedicated clock lane, achieving 7× serialization per channel.
It uses current-mode LVDS drivers with 250–450 mV differential output voltage and ±35 mV matching between complementary outputs, ensuring low EMI and robust noise immunity. The device supports precise pulse positioning (e.g., TPPos0 = −0.4 to 0.3 ns at 66 MHz) and maintains channel-to-channel skew ≤250 ps, critical for maintaining receiver sampling margin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0 V to 3.6 V - Enables direct compatibility with standard 3.3 V logic systems without level-shifting. |
| Data Throughput | 1.386 Gbps - Achieved at 66 MHz clock rate, supporting real-time video and high-bandwidth sensor data transport. |
| Differential Output Swing | 250–450 mV - Ensures reliable LVDS signaling with low EMI and >200 mV noise margin against differential interference. |
| Operating Temperature | −40°C to +85°C - Qualified for industrial and embedded environments including automotive infotainment displays. |
| Power Consumption | 42–55 mA typical at 66 MHz - Delivers <250 mW chipset power with power-down mode reducing total draw to <0.5 mW. |
| ESD Rating | >7 kV HBM - Provides robust handling protection during PCB assembly and system integration. |
| Channel Skew | ≤250 ps - Guarantees tight timing alignment across all LVDS data lanes for accurate multi-bit recovery at receiver. |
Pinout & Package
DS90CR215MTD/NOPB is housed in a low-profile 48-lead TSSOP package (Package Code DGG0048A), with exposed thermal pad not electrically connected. Pin assignments are validated per TI SNLS129D datasheet Figure 3 and Pin Descriptions table.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TxIN[0:20] | Parallel CMOS/TTL data input | 21-bit wide synchronous bus accepting rising-edge-strobed TTL/CMOS signals; unused pins must be tied to GND. |
| TxCLK IN | Input clock reference | Rising edge serves as data strobe; accepts 3.3 V TTL levels; requires <5 ns transition time for stable PLL lock. |
| TxOUT+[0:2], TxOUT−[0:2] | LVDS differential data outputs | Three 7-bit LVDS data lanes (21 bits total); each pair requires 100 Ω termination at receiver side. |
| TxCLK OUT+, TxCLK OUT− | LVDS differential clock output | Transmits synchronized clock alongside data; enables receiver clock recovery without separate reference. |
| PWR DWN | Active-low power-down control | Drives all LVDS outputs into high-impedance state; reduces supply current to <55 μA when asserted. |
| VCC, LVDS VCC, PLL VCC | Separate power domains | Independent 3.3 V supplies for logic, LVDS drivers, and PLL reduce noise coupling and improve jitter performance. |
| GND, LVDS GND, PLL GND | Isolated ground returns | Dedicated ground paths prevent switching noise from corrupting PLL or LVDS signal integrity. |
Key Features
| Feature | Design Value |
|---|---|
| 21-bit parallel-to-serial conversion | Reduces 21-signal parallel bus to only four LVDS differential pairs (3 data + 1 clock), cutting cable count by ~80%. |
| Rising-edge data strobe | Synchronizes all 21 input bits on TxCLK IN rising edge, eliminating setup/hold timing constraints on source logic. |
| Integrated PLL with no external components | Eliminates need for external crystal or loop filter, simplifying BOM and board layout while maintaining <250 ps jitter. |
| LVDS compliance per TIA/EIA-644 | Ensures interoperability with industry-standard LVDS receivers and guarantees common-mode range of +1.0 V around +1.2 V. |
| Power-down mode with <0.5 mW consumption | Enables dynamic power gating in battery-sensitive or thermally constrained systems without disrupting system-level reset sequencing. |
Applications
| Flat-Panel Display Interface | Industrial Machine Vision Camera |
|---|---|
|
Use Scenario: Transmitting RGB pixel data and timing signals from graphics controller to LCD or OLED panel over flexible cable. IC Role / Device Role / Timing Role: DS90CR215MTD/NOPB acts as serializer converting 21-bit parallel video bus into compact LVDS link; rising-edge strobe aligns pixel data to display clock. Use Value: Reduces connector size and EMI vs. parallel TTL interface, enabling thinner displays and longer cable runs up to 5 m using Twin-Coax. |
Use Scenario: High-speed image sensor data transmission from CMOS image sensor to FPGA-based frame grabber in factory automation. IC Role / Device Role / Timing Role: DS90CR215MTD/NOPB serializes raw Bayer-pattern pixel data at 66 MHz, preserving timing integrity for real-time processing. Use Value: Maintains sub-nanosecond pulse positioning accuracy (TPPos0 = −0.4 to 0.3 ns) to ensure error-free pixel capture at full resolution. |
| Medical Imaging Equipment | Avionics Video Distribution |
|
Use Scenario: Transmitting diagnostic ultrasound or endoscope video over shielded cable within compact medical chassis. IC Role / Device Role / Timing Role: DS90CR215MTD/NOPB provides galvanically isolated, low-noise serial link between imaging ASIC and display subsystem. Use Value: 290 mV LVDS swing and >7 kV ESD rating support safe, reliable operation in safety-critical environments with strict EMC requirements. |
Use Scenario: Distributing cockpit display video from central processor to multiple multifunction displays in aircraft avionics. IC Role / Device Role / Timing Role: DS90CR215MTD/NOPB serves as ruggedized serializer meeting DO-160 lightning-induced transient and temperature specs. Use Value: −40°C to +85°C operation and 250 ps channel skew enable deterministic timing across vibration-prone airframe wiring harnesses. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CR215MTDX/NOPB | Same die and functionality; differs only in packaging (1000-piece tape-and-reel vs. 38-piece tube). | No functional difference; selected for automated SMT production vs. prototyping or low-volume builds. | Choose DS90CR215MTDX/NOPB for volume manufacturing; DS90CR215MTD/NOPB for evaluation or small-batch assembly. |
| DS90CR285MTD/NOPB | 28-bit serializer (7 more data bits); same 48-pin TSSOP package but different pin mapping and higher bandwidth (1.848 Gbps @ 66 MHz). | Supports wider parallel buses (e.g., 28-bit RGB+sync) and higher-resolution displays; not pin-compatible. | Select DS90CR285MTD/NOPB only when 28-bit data width is required; DS90CR215MTD/NOPB remains optimal for 21-bit legacy display interfaces. |
Compared with DS90CR215MTDX/NOPB, the DS90CR215MTD/NOPB offers identical electrical performance in tube packaging for flexibility in low-volume use; compared with DS90CR285MTD/NOPB, it delivers precise 21-bit serialization with lower power and simpler layout, avoiding unnecessary complexity for standard VGA/XGA display links.
Availability
DS90CR215MTD/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, industrial machine vision systems, and medical imaging equipment requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for DS90CR215MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of experience in high-speed interface solutions.
The DS90CR215MTD/NOPB belongs to TI's Channel Link family of LVDS serializers, designed specifically for replacing bulky parallel buses in display, imaging, and industrial video applications with robust, low-EMI differential links.
FAQ
What is the maximum data rate supported by the DS90CR215MTD/NOPB?
The DS90CR215MTD/NOPB supports a maximum data throughput of 1.386 Gbps at a 66 MHz transmit clock frequency. This is achieved by serializing 21 bits per clock cycle across three LVDS data lanes (7 bits per lane) plus one LVDS clock lane. The device is characterized for stable operation up to this rate across the full −40°C to +85°C temperature range, with verified pulse positioning and skew margins per TI SNLS129D.
Does the DS90CR215MTD/NOPB require external components for PLL operation?
No, the DS90CR215MTD/NOPB integrates a fully self-contained PLL that requires no external crystals, capacitors, or resistors. As confirmed in the TI SNLS129D datasheet, the PLL locks to the incoming TxCLK IN signal and generates the necessary internal timing for serialization without any external components-reducing BOM cost and board area while improving reliability.
What is the recommended termination for DS90CR215MTD/NOPB LVDS outputs?
The DS90CR215MTD/NOPB LVDS outputs require a 100 Ω differential termination resistor placed as close as possible to the receiver inputs (e.g., DS90CR216). This value matches the nominal differential impedance of standard LVDS cabling and ensures proper signal integrity. TI explicitly states no pull-up or pull-down resistors are needed, and surface-mount resistors are preferred to minimize parasitic inductance.
Can the DS90CR215MTD/NOPB operate with a 5 V input interface?
No, the DS90CR215MTD/NOPB accepts only 3.3 V CMOS/TTL input levels and is not 5 V tolerant. Its VIH minimum is 2.0 V and VIL maximum is 0.8 V under 3.3 V supply, and applying 5 V signals risks permanent damage. For legacy 5 V systems, TI recommends upgrading to the 3.3 V supply domain and using level translators if interfacing with older controllers.
How does the power-down mode affect DS90CR215MTD/NOPB outputs and supply current?
When PWR DWN is asserted low, the DS90CR215MTD/NOPB places all LVDS outputs (TxOUT± and TxCLK OUT±) into high-impedance TRI-STATE and reduces total supply current to <55 μA (typical). This mode preserves signal integrity on shared buses and cuts static power to near-zero, making it ideal for dynamic power management in portable or thermally sensitive systems using DS90CR215MTD/NOPB.
DS90CR215MTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CR215MTD/NOPB FAQ
1.How can I place an order for DS90CR215MTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CR215MTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CR215MTD/NOPB reliable?
The price and inventory of DS90CR215MTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CR215MTD/NOPB is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CR215MTD/NOPB transactions.
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DS90CR215MTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CR215MTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CR215MTD/NOPB?
For technical support, including DS90CR215MTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CR215MTD/NOPB requirements.
6.How does Aetrix verify that DS90CR215MTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CR215MTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CR215MTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CR215MTD/NOPB?
All DS90CR215MTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CR215MTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CR215MTD/NOPB part is unused and in its original packaging.
Return procedure for DS90CR215MTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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