Texas Instruments DS90CR216MTDX

Overview

DS90CR216MTDX from Texas Instruments is a 21-bit LVDS receiver IC that converts three LVDS data streams and one LVDS clock stream back into parallel CMOS/TTL data, supporting up to 66 MHz clock frequency, 1.386 Gbps aggregate throughput, and −40°C to +85°C operation in a 48-lead TSSOP package. It serves as the receiver half of the DS90CR215/DS90CR216 Channel Link chipset for high-speed serial interface applications such as flat-panel display interconnects and industrial camera links.

For engineers reviewing the DS90CR216MTDX datasheet, DS90CR216MTDX pinout, DS90CR216MTDX application, or DS90CR216MTDX equivalent, this page delivers verified technical context, real-world timing margins, confirmed power-down behavior, exact LVDS input threshold specs, and validated alternative receivers compatible with 21-bit rising-edge strobe LVDS systems.

Technical Context

The DS90CR216MTDX implements a PLL-based clock recovery architecture that locks to the incoming LVDS clock (RxCLK IN±) and regenerates a clean TTL-level RxCLK OUT with rising-edge strobe alignment to recovered data. It supports differential input thresholds of ±100 mV around a +1.2 V common-mode voltage and tolerates up to 400 ps inter-pair skew at 66 MHz while maintaining ≥400 ps valid sampling margin (RSKM).

Its 21 CMOS/TTL outputs (RxOUT) are actively driven during normal operation and forced low during power-down mode (PWR DWN = low), unlike legacy 5V Channel Link receivers. The device requires external 100 Ω termination across each LVDS input pair and draws 78–105 mA typical supply current at 66 MHz over full temperature range.

Key Specifications

Pinout & Package

DS90CR216MTDX is housed in a 48-lead Thin Shrink Small Outline Package (TSSOP), package code DGG0048A, with exposed thermal pad (not electrically connected). Pin spacing is 0.5 mm; body dimensions are 12.5 mm × 6.1 mm × 1.2 mm. Thermal resistance θ_JA is 52.3°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 21-bit LVDS receiver applications.

Compared with DS90CR216MTD/NOPB, DS90CR216MTDX/NOPB.B offers identical performance in optimized tape-and-reel format for high-volume placement, while SN65LVDS32 serves fundamentally different system architectures lacking integrated clock recovery and multi-bit deserialization.

Availability

DS90CR216MTDX is available at Aetrix Electronics and suitable for flat-panel display interfaces, machine vision camera links, medical imaging backplanes, and industrial control bus extensions requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for DS90CR216MTDX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS90CR216MTDX belongs to TI's Channel Link serializer/deserializer product line, designed specifically for noise-immune, high-bandwidth, low-pin-count interconnects between graphics controllers and displays or between sensors and processors.

FAQ

What is the primary function of the DS90CR216MTDX in a Channel Link system?

The DS90CR216MTDX functions as the receiver IC in the DS90CR215/DS90CR216 Channel Link chipset. It accepts three LVDS data streams and one LVDS clock stream, recovers the embedded clock via an internal PLL, and reconstructs 21 bits of parallel CMOS/TTL data synchronized to the rising edge of RxCLK OUT. Its role is essential for high-speed, low-skew serial-to-parallel conversion in display and imaging interfaces.

Does the DS90CR216MTDX require external components for clock recovery?

No, the DS90CR216MTDX integrates a fully self-contained PLL for clock recovery and requires no external capacitors, resistors, or crystals. The PLL locks directly to the incoming LVDS clock (RxCLK IN±) and generates a clean, low-jitter RxCLK OUT signal. External 100 Ω termination resistors are required across each LVDS input pair, but no additional timing components are needed for PLL operation.

How does the DS90CR216MTDX handle power-down mode, and what happens to its outputs?

When the PWR DWN pin is asserted low, the DS90CR216MTDX enters power-down mode, reducing supply current to <55 μA. Crucially, all 21 RxOUT outputs are actively driven low - unlike earlier 5V Channel Link receivers that held previous states. This ensures predictable, safe logic levels on downstream buses during standby or fault conditions, simplifying system-level power management design.

What is the maximum cable skew the DS90CR216MTDX can tolerate at 66 MHz operation?

At 66 MHz, the DS90CR216MTDX guarantees a minimum receiver skew margin (RSKM) of 400 ps. This margin accounts for transmitter pulse position variation, internal setup/hold windows, and allows for inter-pair cable skew, inter-symbol interference, and clock jitter up to 250 ps. To maintain this margin, TI recommends keeping cable skew below 150 ps for reliable operation at full speed.

Is the DS90CR216MTDX pin-compatible with the older DS90CR214 5V receiver?

The DS90CR216MTDX is functionally backward compatible with the DS90CR214 but not pin-compatible due to differences in supply architecture: DS90CR216MTDX uses separate VCC, LVDS VCC, and PLL VCC pins, whereas DS90CR214 uses a single 5V supply. Migration requires PCB redesign to accommodate three independent 3.3V rails and level-shifting of transmitter-side inputs, though logic pin mapping (RxIN±, RxOUT, PWR DWN) remains consistent.