Texas Instruments DS90CR216MTDX-TI

Overview

DS90CR216MTDX-TI from Texas Instruments is a 21-bit LVDS receiver IC for Channel Link serial interface systems, converting three LVDS data streams and one LVDS clock stream back into parallel 21-bit CMOS/TTL data at up to 66 MHz clock rate, delivering 1.386 Gbps throughput with 290 mV differential swing and −40°C to +85°C operation. It serves as the receive-side companion to DS90CR215 in high-speed video, flat-panel display, and industrial imaging interconnects.

For engineers reviewing the DS90CR216MTDX-TI datasheet, DS90CR216MTDX-TI pinout, DS90CR216MTDX-TI application, or DS90CR216MTDX-TI equivalent, this page delivers verified technical context, exact pin functions, real-world timing margins (e.g., 400 ps skew margin at 66 MHz), supply current specs (78–105 mA worst-case), and validated alternatives for system-level design and BOM replacement.

Technical Context

The DS90CR216MTDX-TI implements a PLL-based clock recovery architecture that locks to the embedded LVDS transmit clock (TxCLK OUT±) and reconstructs a clean TTL clock (RxCLK OUT) synchronized to recovered data. Its input stage accepts three differential LVDS data pairs (RxIN± ×3) and one differential LVDS clock pair (RxCLK IN±), all compliant with TIA/EIA-644.

It outputs 21 TTL-level data bits (RxOUT[0:20]) and one TTL clock (RxCLK OUT), with rising-edge strobing. Power-down mode forces all RxOUT pins low and draws <55 μA, while internal termination support and 100 mV differential threshold enable robust sampling under interconnect skew and jitter ≤250 ps.

Key Specifications

Pinout & Package

DS90CR216MTDX-TI uses a 48-lead TSSOP package (Package Drawing DGG0048A), with dedicated power domains for TTL I/O (VCC/GND), LVDS inputs (LVDS VCC/LVDS GND), and PLL (PLL VCC/PLL GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CR216MTD/NOPB, DS90CR216MTDX-TI offers assured long-term supply and logistics scalability; compared with SN65LVDS32DR, it delivers complete Channel Link protocol handling-including clock recovery, 21-bit parallel output, and skew-tolerant timing-eliminating need for external logic or custom firmware.

Availability

DS90CR216MTDX-TI is available at Aetrix Electronics and suitable for flat-panel display interfaces, industrial camera links, medical imaging backplanes, and automotive infotainment video systems requiring stable component supply, long-lifecycle assurance, and traceable sourcing.

Supply support for DS90CR216MTDX-TI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in high-speed interface solutions.

DS90CR216MTDX-TI belongs to TI's Channel Link family, designed specifically for high-bandwidth, low-skew, low-EMI serial interconnects in display, imaging, and industrial video applications where cable reduction and timing integrity are critical.

FAQ

What is the primary function of the DS90CR216MTDX-TI in a Channel Link system?

The DS90CR216MTDX-TI is a 21-bit LVDS receiver that deserializes three LVDS data streams and one LVDS clock stream into parallel 21-bit CMOS/TTL data and a synchronized TTL clock output. It works exclusively with the DS90CR215 transmitter to replace wide parallel buses with compact differential cabling. The DS90CR216MTDX-TI performs full clock recovery using an integrated PLL and delivers precise timing alignment essential for video and imaging applications.

Does the DS90CR216MTDX-TI require external components for PLL operation?

No, the DS90CR216MTDX-TI's PLL requires no external capacitors, resistors, or crystals. It locks directly to the incoming LVDS clock (RxCLK IN±) and generates a clean, low-jitter RxCLK OUT synchronized to recovered data. This self-contained PLL design simplifies layout, reduces BOM count, and eliminates tuning steps-confirmed in TI's SNLS129D datasheet Section "Features" and Figure 15 (PLL Set Time).

What is the maximum supported clock frequency and corresponding data throughput for DS90CR216MTDX-TI?

The DS90CR216MTDX-TI supports a maximum transmit clock frequency of 66 MHz, yielding a total data throughput of 1.386 Gbps (173 MB/s). This is achieved by sampling 21 bits per clock cycle across three LVDS lanes, each carrying 7 bits per cycle. The specification is validated across −40°C to +85°C and documented in the "Features" section and Electrical Characteristics tables of the DS90CR216MTDX-TI datasheet.

How does the DS90CR216MTDX-TI handle power-down mode, and what is its current draw in that state?

When the PWR DWN pin is driven low, the DS90CR216MTDX-TI places all 21 RxOUT pins in a forced logic-low state and reduces total supply current to ≤55 μA. This mode is fully specified in the Electrical Characteristics table under ICCRZ (Receiver Supply Current Power Down). The DS90CR216MTDX-TI exits power-down within 1 μs (RPDD parameter), enabling rapid wake-up in responsive display or imaging systems.

Is the DS90CR216MTDX-TI pin-compatible with earlier 5 V Channel Link receivers like DS90CR214?

No, the DS90CR216MTDX-TI is not pin-compatible with DS90CR214. While functionally backward compatible in protocol (same 21-bit mapping and timing structure), it uses a different pinout optimized for 3.3 V operation, separate power domains (LVDS VCC, PLL VCC, VCC), and added ground pins. The DS90CR216MTDX-TI datasheet explicitly states "backward compatible" refers to system-level interoperability-not mechanical or electrical pin-for-pin replacement.