Texas Instruments DS90CR217MTD

Overview

DS90CR217MTD from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS transmitter IC that converts 21-bit parallel CMOS/TTL data into three LVDS data streams plus one LVDS clock stream, supporting up to 85 MHz shift clock and 1.785 Gbps aggregate throughput for high-speed serial interface applications in flat-panel display interconnects and embedded video links.

For engineers reviewing the DS90CR217MTD datasheet, DS90CR217MTD pinout, DS90CR217MTD application, or DS90CR217MTD equivalent, key selection criteria include rising-edge data strobe timing, 345 mV typical LVDS swing, ±1 V common-mode input range, TSSOP-48 package compatibility, and TIA/EIA-644 LVDS compliance for noise-immune board-to-board transmission.

Technical Context

The DS90CR217MTD implements a PLL-based transmit clock generation architecture with no external components required, synchronizing 21-bit parallel inputs to a single TTL clock input whose rising edge acts as the data strobe. It drives four differential LVDS outputs: three data lanes (TxOUT+, TxOUT−) and one clock lane (TxCLK OUT+, TxCLK OUT−), each terminated with 100 Ω differential impedance.

It operates across −10°C to +70°C ambient temperature with 3.0–3.6 V supply, delivers 39–57 mA supply current at 85 MHz, and achieves ≤2 ns cycle-to-cycle jitter on TxCLK IN while maintaining channel-to-channel skew under 90 ps - critical for reliable sampling at the receiver end of high-speed serialized links.

Key Specifications

Pinout & Package

DS90CR217MTD is housed in a low-profile 48-lead TSSOP package (NS package code MTD48), with dedicated power domains for TTL logic (VCC/GND), PLL (PLL VCC/PLL GND), and LVDS drivers (LVDS VCC/LVDS GND) to minimize noise coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90CR217MTD, DS90CR215MTD offers identical interface and timing but reduced data width, while SN65LVDS31DR lacks serialization capability entirely - making DS90CR217MTD uniquely suited for compact, self-clocked 21-bit video links.

Availability

DS90CR217MTD is available at Aetrix Electronics and suitable for LCD panel interconnects, embedded video transport, medical imaging display interfaces, and avionics video distribution requiring stable component supply and long-term manufacturability.

Supply support for DS90CR217MTD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains its high-performance analog and interface product lines, including legacy Channel Link devices.

The DS90CR217MTD belongs to TI's Channel Link serializer family, designed specifically for high-bandwidth, low-EMI parallel-to-LVDS conversion in display, imaging, and real-time video systems.

FAQ

What is the maximum clock frequency supported by the DS90CR217MTD?

The DS90CR217MTD supports a maximum shift clock frequency of 85 MHz, enabling 21-bit parallel data sampling and serialization at 595 Mbps per LVDS lane. At this rate, the device achieves 1.785 Gbps aggregate throughput and 223 MB/s bandwidth. Operation above 85 MHz is not specified and may violate setup/hold timing or exceed jitter budgets.

Does the DS90CR217MTD require external components for PLL operation?

No, the DS90CR217MTD integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. Its internal PLL locks to the incoming TxCLK IN signal and generates the precise timing needed for LVDS serialization and clock embedding - simplifying design and reducing bill-of-materials cost.

How is power sequencing managed on the DS90CR217MTD?

The DS90CR217MTD powers up with outputs in TRI-STATE until VCC reaches 2 V; clock and data begin toggling 10 ms after VCC exceeds 3 V and PWR DWN is above 1.5 V. The PWR DWN pin must be asserted low before removing TxCLK IN and held low until clock reapplication to ensure proper reset and PLL relock - preventing metastability or undefined output states.

What is the recommended termination for DS90CR217MTD LVDS outputs?

Each DS90CR217MTD LVDS differential pair - including three data lanes and one clock lane - requires a 100 Ω termination resistor placed across the true/complement lines at the receiver end. The resistor value should match the cable's differential characteristic impedance (typically 90–120 Ω), and surface-mount construction is mandatory to minimize stub inductance and preserve signal integrity.

Can unused TxIN pins on the DS90CR217MTD be left floating?

Yes, unused TxIN pins on the DS90CR217MTD may be left unconnected (no connect), though tying them to GND is also acceptable and electrically benign. Neither option affects device operation, as inputs are CMOS with high-impedance structure and negligible leakage current - no pull-up or active biasing is required.