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Texas Instruments DS90CR217MTD/NOPB
- Part No.:
- DS90CR217MTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CR217MTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:153
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Product details
Overview
DS90CR217MTD/NOPB from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS transmitter IC that converts 21-bit parallel CMOS/TTL data into three differential LVDS data streams plus one LVDS clock stream, supporting up to 85 MHz shift clock and 1.785 Gbps aggregate throughput for high-speed serial link applications in display interfaces and embedded video systems.
For engineers reviewing the DS90CR217MTD/NOPB datasheet, DS90CR217MTD/NOPB pinout, DS90CR217MTD/NOPB application, or DS90CR217MTD/NOPB equivalent, this device is selected for EMI-sensitive, space-constrained board-to-board or cable-based video data transmission where narrow bus width, low swing (345 mV typ), and precise timing alignment (±0.2 ns pulse position accuracy at 85 MHz) are critical.
Technical Context
The DS90CR217MTD/NOPB implements a rising-edge data strobe architecture synchronized to TxCLK IN, with internal PLL generating a phase-locked transmit clock distributed over a dedicated LVDS pair. It supports 20–85 MHz input clock range and delivers deterministic channel-to-channel skew ≤90 ps at 85 MHz.
Its LVDS drivers meet TIA/EIA-644 standards with ±1 V common-mode range centered at +1.2 V, 250–450 mV differential output voltage, and 0.75–1.5 ns transition times. The PLL requires no external components and achieves lock within 10 ms.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Ensures compatibility with standard +3.3 V logic rails and noise margin under 100 mVPP supply ripple. |
| Data Rate per Channel | 595 Mbps - Enables 21-bit parallel data serialization at 85 MHz clock, reducing interconnect count by 7× vs. TTL. |
| Aggregate Throughput | 1.785 Gbps - Supports real-time transmission of high-resolution video (e.g., WXGA @ 60 Hz) over compact cables. |
| Differential Output Swing | 250–450 mV (typ 345 mV) - Minimizes EMI and power consumption while maintaining noise immunity in noisy environments. |
| Input Setup/Hold Time | TSTC = 2.5 ns, THTC = 0 ns at 85 MHz - Enables reliable sampling of fast TTL inputs without external timing constraints. |
| Channel Skew | ≤90 ps - Guarantees sufficient sampling window at receiver for robust data recovery across all 21 bits. |
| Power-Down Current | 10–55 µA - Reduces system standby power when link is inactive, critical for portable or thermally constrained designs. |
Pinout & Package
DS90CR217MTD/NOPB is housed in a low-profile 48-lead TSSOP package (NS package code MTD48), measuring 12.5 mm × 6.1 mm × 1.2 mm, with exposed thermal pad for enhanced heat dissipation in continuous operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TxIN[0:20] | CMOS/TTL Data Input | 21-bit parallel data bus sampled on rising edge of TxCLK IN; unused pins may be tied to GND or left floating. |
| TxCLK IN | CMOS/TTL Clock Input | Rising-edge strobe signal; must be present before PWR DWN deassertion; stops PLL if halted during operation. |
| PWR DWN | Active-Low Power-Down Control | Tri-states all LVDS outputs and reduces supply current to µA range; must be held low until clock re-established after loss. |
| TxOUT+[0:2], TxOUT−[0:2] | LVDS Data Output Pairs | Three differential pairs carrying serialized 21-bit data (7 bits/pair); require 100 Ω termination at receiver. |
| TxCLK OUT+, TxCLK OUT− | LVDS Clock Output Pair | Dedicated differential clock channel synchronized to data; enables source-synchronous recovery at receiver. |
| VCC, PLL VCC, LVDS VCC | Separate Power Rails | Isolated supplies reduce noise coupling: logic (VCC), PLL (PLL VCC), and LVDS drivers (LVDS VCC). |
| GND, PLL GND, LVDS GND | Separate Ground Returns | Dedicated ground paths prevent return-current interference between logic, PLL, and high-speed analog output sections. |
Key Features
| Feature | Design Value |
|---|---|
| Rising-edge data strobe architecture | Eliminates need for separate enable/control signals; simplifies timing interface and reduces FPGA/ASIC pin count. |
| No external PLL components required | Reduces BOM cost and PCB area; improves reliability by removing discrete capacitors or resistors from clock generation path. |
| ±1 V common-mode input range | Accommodates ground potential differences up to 2 V between transmitter and receiver boards, easing system-level integration. |
| 345 mV typical LVDS swing | Lowers radiated emissions and dynamic power versus higher-swing alternatives, meeting stringent EMI requirements. |
| Best-in-class TxIN setup time (2.5 ns) | Enables direct connection to high-speed microcontrollers or FPGAs without additional timing buffers or delay matching. |
Applications
| Display Interface Link | Industrial Camera Interface |
|---|---|
|
Use Scenario: Transmitting RGB video data from GPU or SoC to LCD panel over flexible flat cable in thin client or kiosk displays. IC Role / Device Role / Timing Role: Parallel-to-serial converter providing source-synchronous LVDS clock and data for pixel-accurate timing. Use Value: Replaces 21+ single-ended traces with only four differential pairs, cutting cable width by >60% and eliminating skew-induced color artifacts. |
Use Scenario: High-speed image sensor data transport from CMOS image sensor to FPGA-based vision processor in factory automation cameras. IC Role / Device Role / Timing Role: Serializer enabling deterministic latency and jitter-controlled sampling of raw Bayer data at up to 85 MHz pixel clock. Use Value: Maintains <±0.2 ns pulse position accuracy across all 21 bits, preserving pixel alignment critical for sub-pixel interpolation algorithms. |
| Medical Imaging Backplane | Avionics Video Distribution |
|
Use Scenario: Transmitting uncompressed ultrasound or endoscope video across backplane connectors in portable diagnostic equipment. IC Role / Device Role / Timing Role: EMI-hardened serializer operating in mixed-signal medical enclosures with strict CISPR 22 Class B compliance. Use Value: 345 mV LVDS swing and differential signaling achieve >40 dB common-mode rejection, preventing RF interference with sensitive analog front-ends. |
Use Scenario: Distributing synthetic vision or map data from mission computer to cockpit displays in certified avionics systems. IC Role / Device Role / Timing Role: Robust serializer supporting extended temperature range (−10°C to +70°C) and latch-up tolerance >±300 mA. Use Value: Withstands transient ESD >7 kV (HBM) and operates reliably under vibration/shock conditions without bit errors or lock loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CR215MTD/NOPB | 18-bit version (3 × 6-bit channels); same 85 MHz max clock and TSSOP-48 package. | Suitable for lower-resolution displays or reduced-data-rate imaging sensors. | Select when 21-bit width is unnecessary-reduces pin count and routing complexity without sacrificing clock rate or layout footprint. |
| SN65LVDS31DR | Quad LVDS line driver (no serialization logic); requires external parallel-to-serial logic; SOIC-16 package. | Used in custom serializer implementations where FPGA handles framing and clock embedding. | Choose only when full control over serialization protocol is needed; adds design complexity and increases component count versus integrated solution. |
Compared with DS90CR217MTD/NOPB, DS90CR215MTD/NOPB offers identical timing and packaging but reduced data width, while SN65LVDS31DR shifts serialization responsibility to the system controller-making DS90CR217MTD/NOPB optimal for turnkey, low-risk LVDS link deployment.
Availability
DS90CR217MTD/NOPB is available at Aetrix Electronics and suitable for display interface links, industrial camera interfaces, and medical imaging backplanes requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for DS90CR217MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired National Semiconductor in 2011 and maintains its legacy high-speed interface portfolio, emphasizing signal integrity, low-power design, and industrial reliability.
The DS90CR217MTD/NOPB belongs to TI's Channel Link family-designed specifically for EMI-constrained, high-bandwidth parallel-to-serial conversion in display, imaging, and instrumentation systems where cable size and timing precision are critical.
FAQ
What is the maximum supported clock frequency for DS90CR217MTD/NOPB?
The DS90CR217MTD/NOPB supports a maximum shift clock frequency of 85 MHz, enabling 21-bit parallel data transmission at 595 Mbps per LVDS channel and an aggregate throughput of 1.785 Gbps. Operation above this frequency is not guaranteed and violates the device's AC timing specifications including setup/hold and pulse position tolerances.
Does DS90CR217MTD/NOPB require external components for PLL operation?
No, DS90CR217MTD/NOPB integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. This eliminates tuning complexity and improves startup reliability-the PLL achieves lock within 10 ms after power-up and valid clock application, as specified in the transmitter switching characteristics table.
How is power sequencing handled in DS90CR217MTD/NOPB?
DS90CR217MTD/NOPB requires VCC ≥ 2 V before outputs exit high-impedance state, and clock/data toggling begins only after VCC reaches 3 V and PWR DWN is above 1.5 V. The input clock (TxCLK IN) may be applied before or after power-up, but if applied before, PWR DWN must remain asserted low until clock stabilization to ensure proper PLL reset and lock.
What termination is required for DS90CR217MTD/NOPB LVDS outputs?
Each LVDS differential pair (three data + one clock) requires a 100 Ω termination resistor placed across the true/complement lines at the receiver end. The resistor value should match the cable's differential characteristic impedance (typically 90–120 Ω); surface-mount placement adjacent to receiver pins minimizes stub effects and ensures clean signal integrity.
Can unused TxIN pins on DS90CR217MTD/NOPB be left floating?
Yes, unused TxIN pins on DS90CR217MTD/NOPB may be left unconnected (no connect) or tied to GND-both options are explicitly permitted in the Applications Information section. No pull-up or active biasing is required, as input leakage remains within ±15 µA across operating temperature.
DS90CR217MTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 48-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CR217MTD/NOPB FAQ
1.How can I place an order for DS90CR217MTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CR217MTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CR217MTD/NOPB reliable?
The price and inventory of DS90CR217MTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CR217MTD/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CR217MTD/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CR217MTD/NOPB transactions.
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4.How is shipping managed for DS90CR217MTD/NOPB?
DS90CR217MTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CR217MTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CR217MTD/NOPB?
For technical support, including DS90CR217MTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CR217MTD/NOPB requirements.
6.How does Aetrix verify that DS90CR217MTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CR217MTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CR217MTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CR217MTD/NOPB?
All DS90CR217MTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CR217MTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CR217MTD/NOPB part is unused and in its original packaging.
Return procedure for DS90CR217MTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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