Texas Instruments DS90CR217MTDX/NOPB

Overview

DS90CR217MTDX/NOPB from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS transmitter IC that converts 21-bit parallel CMOS/TTL data into three differential LVDS data streams plus one LVDS clock stream, supporting up to 85 MHz shift clock and 1.785 Gbps aggregate throughput for high-speed serial link applications in flat-panel display interfaces and embedded video systems.

For engineers reviewing the DS90CR217MTDX/NOPB datasheet, DS90CR217MTDX/NOPB pinout, DS90CR217MTDX/NOPB application, or DS90CR217MTDX/NOPB equivalent, key selection criteria include rising-edge data strobe timing, channel-to-channel skew ≤0.2 ns at 85 MHz, ±1 V common-mode input range, 345 mV typical LVDS swing, and compatibility with TIA/EIA-644 LVDS standard.

Technical Context

The DS90CR217MTDX/NOPB implements a PLL-based transmit clock generation architecture with no external components required, synchronizing 21-bit parallel inputs to a single TTL clock input (TxCLK IN) sampled on the rising edge. Its output comprises three 7-bit LVDS data lanes and one dedicated LVDS clock lane, enabling deterministic bit mapping per Figure 8.

It supports 20–85 MHz shift clock frequencies with 50% duty cycle output clock, achieves <2.5 ns setup time and 0 ns hold time relative to TxCLK IN at 85 MHz, and maintains channel-to-channel skew within ±0.2 ns across all LVDS outputs - critical for pixel-aligned video transport over flexible interconnects.

Key Specifications

Pinout & Package

DS90CR217MTDX/NOPB is housed in a low-profile 48-lead TSSOP package (NS package code MTD48), with exposed thermal pad for enhanced heat dissipation in continuous high-speed operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90CR217MTDX/NOPB, DS90CR215MTDX/NOPB offers identical timing and layout compatibility but reduced data width, while SN65LVDS31DR serves a fundamentally different signal-conditioning role without serialization capability or embedded clocking.

Availability

DS90CR217MTDX/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, embedded vision systems, medical imaging backplanes, and automotive infotainment displays requiring stable component supply and long-term obsolescence management.

Supply support for DS90CR217MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains full technical support, documentation, and manufacturing continuity for legacy Channel Link products.

The DS90CR217MTDX/NOPB belongs to TI's high-speed interface portfolio designed specifically for noise-immune, high-bandwidth parallel-to-serial conversion in display and imaging subsystems.

FAQ

What is the maximum supported clock frequency for DS90CR217MTDX/NOPB?

The DS90CR217MTDX/NOPB supports shift clock frequencies from 20 MHz to 85 MHz. At 85 MHz, it delivers 1.785 Gbps aggregate throughput across three LVDS data lanes and one clock lane. Operation above 85 MHz is not characterized or guaranteed per the datasheet.

Does DS90CR217MTDX/NOPB require external components for PLL operation?

No, DS90CR217MTDX/NOPB integrates a fully self-contained PLL with no external capacitors or resistors required. This simplifies design, improves jitter performance, and eliminates tuning steps during production - a key advantage over discrete clock synthesis solutions.

How is clock synchronization achieved in DS90CR217MTDX/NOPB?

DS90CR217MTDX/NOPB uses the rising edge of the TTL-level TxCLK IN signal as a data strobe to sample all 21 TxIN bits simultaneously. The internal PLL generates a phase-aligned LVDS clock (TxCLK OUT±) transmitted alongside the data, enabling synchronous recovery at the receiver without a separate reference clock.

What is the recommended termination for DS90CR217MTDX/NOPB LVDS outputs?

Each LVDS differential pair (including TxCLK OUT±) must be terminated with a 100 Ω resistor across the true and complement lines at the receiver end. The resistor value should match the cable's differential characteristic impedance (typically 90–120 Ω), and surface-mount placement adjacent to receiver pins is mandatory to minimize stub effects.

Can unused TxIN pins on DS90CR217MTDX/NOPB be left floating?

Unused TxIN pins on DS90CR217MTDX/NOPB may be either tied to GND or left unconnected - both configurations are explicitly permitted per the datasheet. Floating inputs do not induce latch-up or excessive current draw due to internal clamping and leakage control.