Texas Instruments DS90CR285MTD

Overview

DS90CR285MTD from Texas Instruments is a +3.3V LVDS transmitter IC that converts 28-bit LVCMOS/LVTTL parallel data into four LVDS differential data streams plus one LVDS clock stream, enabling 1.848 Gbps throughput at 66 MHz clock rate for high-speed serial link applications in flat-panel displays and industrial imaging systems.

For engineers reviewing the DS90CR285MTD datasheet, DS90CR285MTD pinout, DS90CR285MTD application, or DS90CR285MTD equivalent, this device serves as the transmit-side component of the DS90CR285/DS90CR286 Channel Link chipset-requiring precise timing alignment, LVDS termination matching, and TSSOP-56 layout considerations for EMI-sensitive high-bandwidth interconnects.

Technical Context

The DS90CR285MTD implements a rising-edge data strobe architecture synchronized to a single TTL input clock (TxCLK IN), sampling all 28 input bits on each rising edge and multiplexing them across four LVDS data pairs and one LVDS clock pair. Its internal PLL requires no external components and locks within 10 ms.

It supports power-down mode (<0.5 mW total) via active-low PWR DWN pin, tri-states all LVDS outputs, and maintains compatibility with TIA/EIA-644 LVDS standard-including 290 mV typical differential output swing, +1.2 V common-mode voltage, and >7 kV HBM ESD rating.

Key Specifications

Pinout & Package

DS90CR285MTD is housed in a 56-lead Low Profile TSSOP package (Package Drawing DGG), with dedicated power domains for TTL logic (VCC/GND), PLL (PLL VCC/PLL GND), and LVDS drivers (LVDS VCC/LVDS GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90CR287MTD, DS90CR285MTD delivers proven 66 MHz stability with lower power and cost; versus SN65LVDS31DR, it integrates serialization, PLL, and 28-bit width into one TSSOP-56 device-reducing layout complexity and inter-device skew.

Availability

DS90CR285MTD is available at Aetrix Electronics and suitable for flat-panel display interfaces, medical imaging subsystems, and industrial vision systems requiring stable component supply across extended product lifecycles.

Supply support for DS90CR285MTD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 50 years of innovation in high-reliability interface solutions.

The DS90CR285MTD belongs to TI's Channel Link serializer family, designed specifically for high-bandwidth, low-EMI parallel-to-serial conversion in display, imaging, and industrial data acquisition systems.

FAQ

What is the maximum clock frequency supported by DS90CR285MTD?

The DS90CR285MTD is specified for operation up to 66 MHz clock frequency, delivering 1.848 Gbps data throughput. At this rate, it achieves 231 MB/s bandwidth with guaranteed timing margins including ≤250 ps channel-to-channel skew and ≥400 ps receiver skew margin (RSKM). Exceeding 66 MHz violates datasheet AC specifications and may cause bit errors.

Does DS90CR285MTD require external components for its PLL?

No, DS90CR285MTD integrates a fully self-contained PLL that requires no external crystals, capacitors, or resistors. The PLL locks within 10 ms of power-up and maintains stable operation across −40°C to +85°C, eliminating BOM items and layout overhead associated with discrete clock generation circuits.

How should unused TxIN pins be handled on DS90CR285MTD?

All unused TxIN pins on DS90CR285MTD must be tied directly to ground (GND) to prevent floating inputs from injecting noise into the 28-bit parallel bus. Leaving them unconnected risks metastability, increased power consumption, and potential EMI coupling-per TI's official application guidance in SNLS130C Section "UNUSED INPUTS".

What LVDS termination is required at the receiver for DS90CR285MTD output pairs?

A single 100 Ω surface-mount resistor must be placed across each LVDS differential pair (TxOUT+/TxOUT−) at the receiver end-matching the nominal differential impedance of the interconnect cable. TI recommends placing these resistors as close as possible to the DS90CR286MTD RxIN pins to minimize stub length and preserve signal integrity.

Is DS90CR285MTD pin-compatible with DS90CR287MTD?

Yes, DS90CR285MTD and DS90CR287MTD share identical 56-lead TSSOP (DGG) packaging, pin assignment, and power domain layout. This allows drop-in replacement in existing designs when higher bandwidth (up to 85 MHz) is required-provided system-level timing analysis confirms compatibility with the faster variant's reduced setup/hold windows.