My Inquiry
My Account
Texas Instruments DS90CR285MTD/NOPB
- Part No.:
- DS90CR285MTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 56-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CR285MTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 56TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:255
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90CR285MTD/NOPB from Texas Instruments is a +3.3V LVDS transmitter IC that converts 28-bit LVCMOS/LVTTL parallel data into four LVDS differential data streams plus one LVDS clock stream, enabling high-speed serial link transmission at up to 66 MHz clock rate and 1.848 Gbps aggregate throughput. It implements rising-edge data strobe timing, operates from −40°C to +85°C, and targets flat-panel display interconnects and embedded video backplanes.
For engineers reviewing the DS90CR285MTD/NOPB datasheet, DS90CR285MTD/NOPB pinout, DS90CR285MTD/NOPB application, or DS90CR285MTD/NOPB equivalent, this page delivers verified technical context, validated pin functions, confirmed package mapping to 56-lead TSSOP (DGG), real-world skew and timing margins, and two rigorously cross-checked alternative transmitters for Channel Link 28-bit systems.
Technical Context
The DS90CR285MTD/NOPB uses an internal PLL to generate synchronized LVDS output clocks without external components and employs rising-edge sampling of TTL inputs relative to TxCLK IN. Its 28-bit parallel interface maps across seven 4-bit nibbles or configurable groupings, with deterministic pulse positioning per bit (e.g., TPPos0 = −0.4 to 0.3 ns at 66 MHz).
It supports full-channel serialization with 290 mV typical LVDS differential swing, 1.25 V nominal common-mode voltage, and 250 ps maximum channel-to-channel skew (TCCS). Power-down mode reduces total current to <0.5 mW while tri-stating all LVDS outputs, and ESD protection exceeds 7 kV HBM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Operates within standard +3.3V rail tolerance; no level-shifting required for LVTTL/LVCMOS logic. |
| Data Throughput | 1.848 Gbps - Achieved at 66 MHz clock with 28 bits/cycle; enables uncompressed RGB888 video transport over 5-pair cable. |
| Differential Swing | 250–450 mV - Matches TIA/EIA-644 LVDS standard; ensures low EMI and robust noise immunity in noisy environments. |
| Common-Mode Range | +1.125 V to +1.375 V - Centered at +1.2 V; supports ±1.0 V ground offset between transmitter and receiver boards. |
| Operating Temperature | −40°C to +85°C - Qualified for industrial-grade embedded displays, medical monitors, and avionics cabin displays. |
| Power-Down Current | <0.5 mW - Enables rapid system-level power gating without affecting adjacent circuitry or requiring auxiliary sequencing. |
| Channel Skew | ≤250 ps - Limits inter-pair timing misalignment; preserves valid data sampling window at receiver under 66 MHz operation. |
Pinout & Package
DS90CR285MTD/NOPB is housed in a 56-lead Low-Profile TSSOP package (Package Drawing DGG), with dedicated power domains for TTL I/O (VCC/GND), LVDS drivers (LVDS VCC/LVDS GND), and PLL circuitry (PLL VCC/PLL GND) to minimize supply coupling and jitter.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TxIN[0:27] | Input | 28-bit LVCMOS/LVTTL parallel data bus; rising edge of TxCLK IN samples all bits simultaneously. |
| TxCLK IN | Input | TTL clock input; rising edge serves as data strobe; requires ≤5 ns transition time for reliable capture. |
| TxOUT+[0:3], TxOUT−[0:3] | Output | Four LVDS differential data pairs; each carries 7-bit subset of 28-bit input (e.g., TxOUT+0 carries bits 0–6). |
| TxCLK OUT+, TxCLK OUT− | Output | LVDS differential clock pair; phase-aligned to data edges; enables synchronous recovery at DS90CR286 receiver. |
| PWR DWN | Input | Active-low control; asserts tri-state on all LVDS outputs and reduces ICC to <55 μA when pulled low. |
Key Features
| Feature | Design Value |
|---|---|
| Rising-edge data strobe | Synchronizes 28-bit parallel capture to TxCLK IN rising edge-eliminates setup/hold ambiguity in high-speed TTL interfaces. |
| No external PLL components | Integrates fully self-contained PLL; removes BOM cost, layout area, and tuning effort associated with crystal or capacitor networks. |
| 290 mV LVDS swing | Optimizes EMI vs. noise margin trade-off; meets TIA/EIA-644 while enabling >80% cable conductor reduction vs. parallel TTL buses. |
| +1V common-mode range | Supports ≥±1.0 V ground potential difference between boards-critical for long-cable or multi-board chassis applications. |
| 56-pin TSSOP with split supplies | Separates VCC, LVDS VCC, and PLL VCC domains-reduces supply-induced jitter and improves timing stability at 66 MHz. |
Applications
| Flat-Panel Display Interface | Medical Imaging Backplane |
|---|---|
|
Use Scenario: Transmitting RGB888 pixel data and sync signals from GPU or timing controller to LCD driver board over 3–5 meter flex cable. IC Role / Device Role / Timing Role: Parallel-to-serial serializer converting 28-bit pixel + control bus into five LVDS pairs with embedded clock. Use Value: Reduces cable width by 80% versus 28+1 single-ended lines; maintains 1.848 Gbps bandwidth with <250 ps skew at 66 MHz. |
Use Scenario: High-fidelity digital X-ray or MRI image data transfer between acquisition module and display processor in shielded diagnostic cart. IC Role / Device Role / Timing Role: Robust serializer for lossless 12-bit grayscale video streams requiring EMI resilience and thermal stability. Use Value: 7 kV HBM ESD rating and −40°C to +85°C operation ensure reliability in clinical environments with frequent handling and temperature cycling. |
| Avionics Cabin Display | Industrial HMI Video Link |
|
Use Scenario: Interconnecting cockpit multifunction display (MFD) with graphics generation unit across aircraft wiring harnesses. IC Role / Device Role / Timing Role: LVDS transmitter providing deterministic timing, low jitter, and fault-tolerant power-down for safety-critical displays. Use Value: Power-down mode cuts current to <0.5 mW during standby; PLL lock time ≤10 ms enables fast wake-up without frame drop. |
Use Scenario: Connecting PLC-based vision controller to remote operator panel in factory automation with vibration and electrical noise. IC Role / Device Role / Timing Role: Noise-immune serializer for machine vision data over unshielded twisted-pair or twin-coax cabling. Use Value: 290 mV LVDS swing and 100 mV receiver threshold deliver >200 mV differential noise margin-rejecting motor drive interference. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS transmitter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CR287MTD/NOPB | Higher clock support (up to 85 MHz); identical 28-bit architecture and pinout; adds spread-spectrum capability. | Required for >66 MHz pixel clocks (e.g., WUXGA @ 75 Hz); not drop-in for legacy 66 MHz designs due to different PLL behavior. | Select DS90CR287MTD/NOPB only when higher bandwidth or EMI reduction via spread spectrum is needed. |
| SN65LVDS31DGGR | 4-channel LVDS transmitter; no integrated clock channel; requires external clock routing; lower integration. | Suitable for custom protocols where clock and data are routed separately; lacks Channel Link framing and synchronization. | Choose SN65LVDS31DGGR only for non-Channel Link systems needing discrete LVDS line drivers without embedded clock. |
Compared with DS90CR285MTD/NOPB, DS90CR287MTD/NOPB offers higher speed but requires PLL revalidation, while SN65LVDS31DGGR provides modular LVDS drive but demands external clock management and increases PCB routing complexity.
Availability
DS90CR285MTD/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, medical imaging backplanes, avionics cabin displays, and industrial HMI video links requiring stable component supply across extended product lifecycles.
Supply support for DS90CR285MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.
The DS90CR285MTD/NOPB belongs to TI's Channel Link serializer family, designed specifically to replace wide parallel buses in display, imaging, and video systems with compact, low-EMI LVDS links.
FAQ
What is the maximum supported clock frequency for DS90CR285MTD/NOPB?
The DS90CR285MTD/NOPB is characterized and specified for operation up to 66 MHz transmit clock frequency, delivering 1.848 Gbps aggregate data throughput. While functional beyond this in some conditions, TI guarantees timing performance-including pulse position accuracy, channel skew, and PLL lock-only up to 66 MHz per the SNLS130C datasheet revision.
Does DS90CR285MTD/NOPB require external termination resistors?
No-DS90CR285MTD/NOPB itself does not require external termination; it drives LVDS outputs actively. However, the receiving end (e.g., DS90CR286) must use a 100 Ω differential termination resistor across each LVDS input pair to match cable impedance and prevent reflections. This resistor is placed at the receiver, not the DS90CR285MTD/NOPB side.
Can DS90CR285MTD/NOPB interface directly with 5V logic?
No-DS90CR285MTD/NOPB inputs are LVCMOS/LVTTL compatible only, with absolute maximum input voltage of VCC + 0.3 V (≤3.6 V + 0.3 V = 3.9 V). Direct connection to 5V logic violates the absolute maximum rating and risks permanent damage. Level-shifting circuitry is required for 5V system interfacing.
How does the power-down mode affect DS90CR285MTD/NOPB outputs?
When PWR DWN is asserted low, DS90CR285MTD/NOPB places all LVDS outputs (TxOUT±[0:3] and TxCLK OUT±) into high-impedance tri-state, reducing total supply current to <0.5 mW. The internal PLL remains active but output drivers are disabled-ensuring zero signal injection into the cable during standby.
Is DS90CR285MTD/NOPB pin-compatible with DS90CR286MTD/NOPB?
No-DS90CR285MTD/NOPB is a transmitter; DS90CR286MTD/NOPB is its complementary receiver. They share the same 56-lead TSSOP package (DGG) and pin count, but pin functions differ entirely: TxIN/TxOUT on DS90CR285MTD/NOPB map to RxIN/RxOUT on DS90CR286MTD/NOPB. They are functionally paired, not pin-compatible replacements.
DS90CR285MTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 56-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 56-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CR285MTD/NOPB FAQ
1.How can I place an order for DS90CR285MTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CR285MTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CR285MTD/NOPB reliable?
The price and inventory of DS90CR285MTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CR285MTD/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CR285MTD/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CR285MTD/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CR285MTD/NOPB?
DS90CR285MTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CR285MTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CR285MTD/NOPB?
For technical support, including DS90CR285MTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CR285MTD/NOPB requirements.
6.How does Aetrix verify that DS90CR285MTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CR285MTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CR285MTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CR285MTD/NOPB?
All DS90CR285MTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CR285MTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CR285MTD/NOPB part is unused and in its original packaging.
Return procedure for DS90CR285MTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90CR285MTD/NOPB Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
