Texas Instruments DS90CR285MTDX

Overview

DS90CR285MTDX from Texas Instruments is a +3.3V LVDS transmitter IC that converts 28-bit LVCMOS/LVTTL parallel data into four LVDS differential data streams plus one LVDS clock stream, enabling 1.848 Gbps throughput at 66 MHz clock rate for high-speed point-to-point interconnects in flat-panel display and imaging systems.

For engineers reviewing the DS90CR285MTDX datasheet, DS90CR285MTDX pinout, DS90CR285MTDX application, or DS90CR285MTDX equivalent, this device is selected for low-EMI serialized video/data links requiring precise timing alignment, sub-250 ps channel skew control, and robust common-mode noise immunity across long cable runs.

Technical Context

The DS90CR285MTDX implements a rising-edge data strobe architecture synchronized to a PLL-generated transmit clock, with all 28 input bits sampled on each rising edge of TxCLK IN. Its LVDS output drivers deliver 290 mV differential swing with ±35 mV matching between complementary outputs and support TIA/EIA-644 compliance.

It operates over −40°C to +85°C with single +3.3V supply, integrates no external PLL components, and provides power-down mode reducing total current to <0.5 mW. Input setup/hold times are 2.5 ns / 0 ns relative to TxCLK IN, and channel-to-channel skew is limited to 250 ps.

Key Specifications

Pinout & Package

DS90CR285MTDX is housed in a 56-lead Low-Profile TSSOP (Package Code DGG), with dedicated power domains for TTL logic (VCC/GND), PLL (PLL VCC/PLL GND), and LVDS I/O (LVDS VCC/LVDS GND).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90CR285MTDX, DS90CR285MTD/NOPB offers identical performance in a smaller reel format, while SN65LVDS31 serves only as a basic LVDS driver without serialization capability - making it unsuitable as a functional replacement in display or imaging links.

Availability

DS90CR285MTDX is available at Aetrix Electronics and suitable for flat-panel display interfaces, medical imaging systems, industrial camera links, and automotive infotainment video requiring stable component supply and long-term industrial-grade availability.

Supply support for DS90CR285MTDX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with broad industrial and automotive design expertise.

The DS90CR285MTDX belongs to TI's Channel Link family of high-speed serializers, engineered specifically for noise-immune, low-skew parallel-to-LVDS conversion in display, imaging, and machine vision applications.

FAQ

What is the maximum supported clock frequency for DS90CR285MTDX?

The DS90CR285MTDX supports a maximum transmit clock frequency of 66 MHz, delivering 1.848 Gbps data throughput and 231 MB/s bandwidth. At this rate, all 28 input bits are sampled on each rising edge of TxCLK IN, and the internal PLL ensures stable clock recovery at the receiver side. Operation beyond 66 MHz is not characterized or guaranteed.

Does DS90CR285MTDX require external components for PLL operation?

No, DS90CR285MTDX requires no external components for PLL operation. Its integrated phase-locked loop generates and recovers the transmit clock without crystals, capacitors, or resistors - simplifying layout and reducing bill-of-materials cost while maintaining jitter performance within specification across temperature and voltage ranges.

How many differential pairs does DS90CR285MTDX use for data and clock transmission?

DS90CR285MTDX uses five differential LVDS pairs: four for data (TxOUT+[0:3]/TxOUT−[0:3]) carrying 7 bits each per clock cycle, and one for the embedded clock (TxCLK OUT+/TxCLK OUT−). This configuration reduces conductor count from 58 (for 28-bit parallel + clock) to just 11 wires including ground, enabling compact cabling solutions.

What is the recommended termination for DS90CR285MTDX LVDS outputs?

DS90CR285MTDX LVDS outputs require 100 Ω differential termination at the receiver end (e.g., DS90CR286), placed as close as possible to RxIN+ and RxIN− pins. The resistor value should match the cable's differential characteristic impedance (typically 90–120 Ω); surface-mount construction is mandatory to minimize stub inductance and preserve signal integrity at 66 MHz.

Can DS90CR285MTDX operate with 5V-tolerant inputs?

No, DS90CR285MTDX inputs are not 5V tolerant. They accept only LVCMOS/LVTTL levels referenced to its +3.3V supply, with VIH ≥ 2.0 V and VIL ≤ 0.8 V. Applying 5V signals risks permanent damage. Level-shifting circuitry is required if interfacing with 5V logic families.